Semiconductor chip and semiconductor package

A semiconductor package comprising:

• a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and top wiring patterns adjacent to the plurality of first pads between the first substrate and the plurality of first pads in a direction perpendicular to the front surface;
• and
• a second chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads,
• wherein the top wiring patterns include a set of first contact patterns contacting a first group of first pads, the first group of first pads including pairs of first pads adjacent to each other in a first direction parallel to the front surface, a set of second contact patterns contacting a second group of first pads, the second group of first pads including pairs of first pads adjacent to each other in the first direction, and at least one trace pattern disposed between adjacent contact patterns of the second contact patterns in the first direction, and
• wherein each first pad of the first group of first pads has a first width in the first direction, and each pad of the second group of first pads has a second width in the first direction, wherein the first width is narrower than the second width.

A semiconductor package comprising:

• at least one semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads,
• wherein the plurality of first pads include first pairs of first pads and second pairs of first pads, each first pad of each first pair having a first area from a plan view and each first pad of each second pair having a second area from the plan view, the second area being different from the first area;
• wherein, within respective first reference regions in the plan view between two pads of respective first pairs of first pads adjacent to each other, respective first top wiring patterns adjacent to the respective first pairs of first pads in a direction perpendicular to the front surface have a first predetermined occupied area,
• wherein, within respective second reference regions in the plan view between two pads of respective second pairs of first pads adjacent to each other, respective second top wiring patterns adjacent to the respective second pairs of first pads in a direction perpendicular to the front surface have a second predetermined occupied area,
• wherein each first reference region has the same area and shape as each second reference region in the plan view,
• wherein each first pair of first pads in a respective reference region in the plan view has an area within the respective reference region proportional to a respective first predetermined occupied area according to a first ratio, and
• wherein each second pair of first pads in a respective reference region in the plan view has an area within the respective reference region proportional to a respective second predetermined occupied area according to the first ratio.