Semiconductor package structure

A semiconductor package structure, comprising:

• a first redistribution layer;
• a first semiconductor die disposed over the first redistribution layer and comprising a first through via;
• a second through via adjacent to the first semiconductor die;
• a second semiconductor die disposed over a first portion of the first semiconductor die and electrically coupled to the first through via and the second through via;
• a third through via disposed over a second portion of the first semiconductor die;
• and
• a second redistribution layer disposed over the second semiconductor die and electrically coupled to the third through via.

A semiconductor package structure, comprising:

• a first redistribution layer;
• a first semiconductor die disposed over the first redistribution layer;
• an interposer disposed over the first redistribution layer and adjacent to the first semiconductor die, wherein the interposer comprises a through via and a deep trench capacitor;
• a second semiconductor die disposed over the interposer and electrically coupled to the through via and the deep trench capacitor;
• a molding material surrounding the first semiconductor die and the interposer;
• and
• a second redistribution layer disposed over the second semiconductor die,
• wherein a bottom surface of the molding material is substantially level with bottom surfaces of the first semiconductor die and the interposer.