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US 12,604,762 B2Granted
Methods and apparatus to reduce thickness of on-package memory architectures
AssigneeIntel Corporation
InventorsEng Huat Goh, Jiun Hann Sir, Poh Boon Khoo
Life of this patent
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Abstract
Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.
Claims22
An apparatus comprising:
- a substrate;
- a processor die mounted to the substrate;
- a memory die mounted to the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die, the memory die including a first side and a second side opposite the first side, the first side of the memory die facing away from the substrate;
- a bonding pad, the memory die electrically coupled to a first surface of the bonding pad, the first surface of the bonding pad facing away from the substrate, the second side of the memory die closer to the substrate than the first surface of the bonding pad is to the substrate;
- and
- a metal stub protruding from a second surface of the bonding pad, the second surface opposite the first surface, an end of the metal stub soldered to a contact pad on the substrate.
3 more elements
An apparatus comprising:
- a substrate;
- a processor die carried by the substrate;
- a memory die carried by the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die;
- a bonding pad, the memory die electrically coupled to a first surface of the bonding pad;
- a metal stub protruding from a second surface of the bonding pad, the second surface opposite the first surface, an end of the metal stub soldered to a contact pad on the substrate;
- and
- a mold compound that encapsulates the memory die and all side walls of the bonding pad, the side walls extending between the first and second surfaces of the bonding pad.
4 more elements
An apparatus comprising:
- a substrate;
- a processor die carried by the substrate;
- a memory die carried by the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die;
- a first bonding pad;
- and
- a second bonding pad, the memory die electrically coupled to at least one of the first bonding pad or the second bonding pad, the memory die laterally between the first bonding pad and the second bonding pad such that the memory die and the first and second bonding pads are in a common plane.
3 more elements
Dependencies are inferred from the claim text.