Semiconductor package

A semiconductor package comprising:

• a circuit board;
• an interposer structure on the circuit board;
• a mold layer on the interposer structure, wherein the mold layer defines a first trench and a plurality of second trenches around the first trench, an area of a cross section of the first trench from a planar viewpoint is greater than an area of a cross section of any one of the plurality of second trenches from the planar viewpoint, a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, an angle defined by a side wall of the first trench and a bottom side of the first trench is greater than or equal to ninety degrees, and an angle defined by a side wall of at least one of the plurality of second trenches and a bottom side of the at least one of the plurality of second trenches is less than or equal to ninety degrees;
• a logic chip in the first trench, the logic chip electrically connected to the interposer structure;
• and
• a memory chip in at least one of the plurality of second trenches, the memory chip electrically connected to the interposer structure.

A semiconductor package comprising:

• a circuit board;
• an interposer structure on the circuit board;
• a mold layer on the interposer structure, the mold layer defining a first trench and a plurality of second trenches around the first trench;
• a logic chip in the first trench, the logic chip electrically connected to the interposer structure;
• a memory chip in at least one of the plurality of second trenches, the memory chip electrically connected to the interposer structure;
• a first connecting member between the circuit board and the interposer structure, the first connecting member electrically connecting the circuit board and the interposer structure;
• a second connecting member between the interposer structure and the logic chip, the second connecting member electrically connecting the interposer structure and the logic chip;
• a third connecting member between the interposer structure and the memory chip, the third connecting member electrically connecting the interposer structure and the memory chip;
• and
• a heat slug on the circuit board, the heat slug covering the logic chip and the memory chip,
• wherein the interposer structure includes an interposer, an interlayer insulating layer on the interposer, redistribution layers in the interlayer insulating layer, and a through via connected to the redistribution layer, and the redistribution layers are electrically connected to the logic chip and the memory chip,
• wherein an area of a cross section of the first trench from a planar viewpoint is greater than an area of a cross section of any one of the plurality of the second trenches from a planar viewpoint,
• a size of the first connecting member is greater than a size of the second connecting member and a size of the third connecting member,
• a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and
• an upper side of the mold layer is on a same plane as an upper side of the logic chip and an upper side of the memory chip.