Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip having a first region and a second region, surrounding the first region, the first semiconductor chip including a passivation layer on an upper surface thereof;
• a semiconductor structure including a second semiconductor chip on the first region of the first semiconductor chip;
• a bump on a lower surface of the semiconductor structure;
• an underfill layer covering a region in which the first semiconductor chip and the semiconductor structure overlap each other in the first region and covering at least a portion of a lower end of a side surface of the semiconductor structure;
• a first organic material layer surrounding a side surface of the underfill layer on the second region;
• and
• an encapsulant covering the semiconductor structure on the first semiconductor chip, an uppermost surface in a vertical direction of the first organic material layer contacting the encapsulant, the vertical direction parallel to a side surface of the first semiconductor chip,
• wherein the first semiconductor chip has an area larger than that of the second semiconductor chip in plan view, and
• wherein the first semiconductor chip includes silicon (Si), the passivation layer contacts the underfill layer on the first region, and the first organic material layer is on the second region.

A semiconductor package comprising:

• a package substrate;
• an interposer substrate on the package substrate and including a silicon (Si) layer;
• a first semiconductor structure on the interposer substrate;
• a second semiconductor structure adjacent to the first semiconductor structure on the interposer substrate, the second semiconductor structure including
• a base chip including a passivation layer on an upper surface thereof,
• a semiconductor chip on the base chip,
• a first semiconductor structure bump on a lower surface of the semiconductor chip,
• a first semiconductor structure underfill layer covering the first semiconductor structure bump and covering the lower surface of the semiconductor chip,
• an encapsulant covering the semiconductor chip on the base chip, and
• a first semiconductor structure organic material layer on the passivation layer, an uppermost surface in a vertical direction of the first semiconductor structure organic material layer contacting the encapsulant, the vertical direction perpendicular the upper surface of the base chip,
• wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the first semiconductor structure underfill layer and a second region, surrounding the first region, and the first semiconductor structure organic material layer is on the second region;
• and
• an interposer encapsulant covering the first semiconductor structure and the second semiconductor structure on the interposer substrate,
• wherein an upper surface of the interposer substrate has a first region in which the first semiconductor structure and the second semiconductor structure are mounted and a remaining second region, and
• the interposer substrate further includes an interposer organic material layer on the remaining second region and including a photosensitive polyimide (PSPI), an uppermost surface in a vertical direction of the interposer organic material layer contacting the interposer encapsulant, the vertical direction perpendicular the upper surface of the interposer substrate.