Integrated circuit (IC) die comprising galvanic isolation capacitor

A method of semiconductor processing, the method comprising:

• forming a first capacitor plate on a first interlayer dielectric (ILD), the first ILD being disposed over a semiconductor substrate;
• forming a second capacitor plate on a second ILD, the second ILD being disposed over the first capacitor plate and the first ILD, a first distance being from a top surface of the first capacitor plate to a bottom surface of the second capacitor plate, the first distance being equal to or greater than 15 μm;
• and
• forming a polyimide layer over the second capacitor plate and the second ILD, a second distance being from a top surface of the second capacitor plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance.

An integrated circuit (IC) die comprising:

• a galvanic isolation capacitor comprising:
• a bottom plate over a semiconductor substrate;
• and
• a top plate over the bottom plate, a first distance being from a top surface of the bottom plate to a bottom surface of the top plate, the first distance being equal to or greater than 15 μm;
• and
• a polyimide layer over the top plate of the galvanic isolation capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance.

An integrated circuit (IC) package comprising:

• a first IC die comprising:
• a first circuit disposed on a first semiconductor substrate;
• a capacitor comprising:
• a bottom plate disposed over the first semiconductor substrate;
• and
• a top plate disposed over the bottom plate, a first distance being from a top surface of the bottom plate to a bottom surface of the top plate;
• and
• a polyimide layer disposed at least partially over the top plate of the capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance;
• and
• a second IC die comprising a second circuit disposed on a second semiconductor substrate, a signal path being electrically coupled between the first circuit and the second circuit, the signal path including the capacitor, the second IC die not including a galvanic isolation capacitor in the signal path, wherein the first IC die further comprises:
• an over-layer dielectric disposed at least partially over the top plate of the capacitor, the top plate of the capacitor being disposed in an uppermost metal level distal from the first semiconductor substrate;
• one or more buffer dielectric layers disposed over the over-layer dielectric;
• and
• a passivation dielectric layer disposed over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.