Metal capping layer for reducing gate resistance in semiconductor devices

A semiconductor structure, comprising:

• a fin extending from a semiconductor substrate;
• a gate stack disposed over a channel region of the fin;
• a glue layer in contact with a top surface of the gate stack;
• a tungsten (W)-containing capping layer disposed over the glue layer, wherein the glue layer surrounds bottom and sidewall surfaces of the W-containing capping layer;
• and
• a contact feature disposed on a top surface of the W-containing capping layer,
• wherein the glue layer and the W-containing capping layer sandwich an air gap.

A semiconductor structure, comprising:

• a semiconductor active region;
• a gate structure disposed over the semiconductor active region;
• a gate spacer disposed along a sidewall of the gate structure;
• a glue layer disposed on a top surface of the gate structure and interfacing the gate spacer;
• a metal capping layer disposed over the glue layer and spaced apart from the gate spacer by the glue layer;
• and
• a gate contact disposed over the metal capping layer,
• wherein a first top surface and a bottom surface of the glue layer are curved toward a first direction,
• wherein a top surface of the metal capping layer is curved toward a second direction opposite to the first direction,
• wherein the top surface of the metal capping layer includes a middle portion and two side portions on two sides of the middle portion,
• wherein the middle portion interfaces with the gate contact, and the two side portions are spaced apart from and at a level lower than a bottom surface of the gate contact.