Reverse embedded power structure for graphical processing unit chips and system-on-chip device packages

A method of manufacturing an IC package, comprising:

• providing a die body, the die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface and the die body including:
• an interconnect region located adjacent to the first body surface, the interconnect region including interconnect dielectric layers with metal lines and vias;
• a transistor region located above the interconnect region, wherein the metal lines and vias make electrical connections to one or more power rails of the transistor region and the power rails are electrically connected to one or more transistors of the transistor region;
• and
• a power region located above the transistor region;
• forming one or more TSVs through the power region including forming a hole through the power region, the hole stopping on one of the power rails of the transistor region and then filling the hole with a metal plug such that an embedded end of the TSVs contact one of the power rails of the transistor region;
• forming an electro-conductive film on the second surface of the die body such that the electro-conductive film contacts an outer end of at least one of the TSVs;
• and
• forming a solder bump on a side edge of the power region and in contact with the electro-conductive film.

A die, comprising:

• a die body, the die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, the die body including:
• an interconnect region located adjacent to the first body surface, the interconnect region including interconnect dielectric layers with metal lines and vias;
• a transistor region located above the interconnect region, wherein the metal lines and vias make electrical connections to one or more power rails of the transistor region and the power rails are electrically connected to one or more transistors of the transistor region;
• a power region located above the transistor region, wherein the power region includes an electro-conductive film on the second body surface, wherein for each one of the TSVs, an outer end of the TSV contacts the electro-conductive film and an embedded end of the TSVs contacts one of the power rails of the transistor region;
• and
• a die substrate wherein the die body is located on a first substrate surface of the die substrate, one or more substrate conductive lines are located on the first substrate surface and a wire bond electrically connects the substrate conductive lines to the electro-conductive film.