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US 12,604,547 B2Granted
Reduced flicker noise transistor layout
AssigneeX-FAB Global Services GmbH
InventorsXuezhou Cao, Shyh Yau Tein, Michaelina Ong
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Abstract
In one aspect, a transistor includes a diffusion region having a drain, a source, and a channel between said drain and source. The transistor further includes an isolation region around said diffusion region for electrically isolating said transistor. In addition, the transistor includes a gate poly overlapping at least a part of said channel, wherein said diffusion region extends laterally beyond said gate poly in a channel width direction.
Claims12
A transistor comprising:
- a diffusion region comprising a drain, a source, and a channel between said drain and source;
- an isolation region around said diffusion region for electrically isolating said transistor;
- and
- a gate poly overlapping at least a part of said channel, wherein said diffusion region extends in a channel width direction, being substantially perpendicular to a direction from said source to said drain, beyond said gate poly,
- wherein the diffusion region comprises heavily doped P+ or N+ regions, and wherein first and second opposing sides of said channel are edged by said heavily doped P+ or N+ regions.
2 more elements
Dependencies are inferred from the claim text.