Semiconductor device having serially connected transistors with disconnected bodies, and method of manufacturing the same

A semiconductor device, comprising:

• a substrate having a first direction and a second direction perpendicular to the first direction, the substrate comprising:
• a first active region, and
• a second active region physically separated, by a first spacing, from the first active region in the second direction;
• a first gate electrode physically extending, continuously in a same layer over the first and second active regions and along the second direction, over the first active region, across the first spacing, and then over the second active region;
• a first transistor configured by the first active region and the first gate electrode, wherein a first body and a first drain of the first transistor are in the first active region;
• a second transistor configured by the second active region and the first gate electrode, wherein a second body of the second transistor is in the second active region;
• a first conductor configured to receive a first reference voltage, wherein the first conductor is connected to the first body of the first transistor;
• and
• a second conductor that connects the second body of the second transistor to the first drain of the first transistor, wherein
• the first conductor is electrically disconnected from the second conductor, and the second conductor is electrically disconnected from the first gate electrode,
• the first active region has a first section that physically extends in the second direction beyond the first gate electrode,
• the first section is aligned with the first gate electrode along the second direction, without overlapping the first gate electrode in a third direction perpendicular to the first and second directions,
• the first conductor physically overlaps the first section in the third direction, and is electrically connected to the first section which provides a connection to the first body, and
• the first gate electrode has a width along the first direction and a length along the second direction, and the length of the first gate electrode is greater than the width of the first gate electrode,
• the semiconductor device further comprising:
• an input/output node;
• a plurality of transistors including the first and second transistors, and third and fourth transistors;
• and
• first and second diodes,
• wherein
• the first transistor has the first body and a first source, wherein the first body and the first source of the first transistor are directly connected to a first reference node which is configured to receive a first reference voltage, wherein
• the first transistor and the second transistor are electrically connected in series,
• the second body of the second transistor is electrically disconnected from the first body of the first transistor,
• a first gate electrode of the first transistor is directly connected to a second gate electrode of the second transistor and to a first node configured to receive a first control signal,
• the first transistor and the second transistor are of a same, first conductivity type, and
• a second drain of the second transistor is directly connected to the input/output node,
• the third transistor has a third body and a third source, wherein the third body and the third source of the third transistor are directly connected to a second reference node which is configured to receive a second reference voltage different from the first reference voltage,
• the fourth transistor has a fourth body, wherein
• the third transistor and the fourth transistor are electrically connected in series,
• the fourth body of the fourth transistor is electrically disconnected from the third body of the third transistor,
• a third gate electrode of the third transistor is directly connected to a fourth gate electrode of the fourth transistor and to a second node configured to receive a second control signal different from the first control signal,
• the third transistor and the fourth transistor are of a same, second conductivity type different from the first conductivity type, and
• a drain of the fourth transistor is directly connected to the input/output node,
• the first diode is connected between the input/output node and the first reference node,
• the second diode is connected between the input/output node and the second reference node, and
• the plurality of transistors is configured to, during an electrostatic discharge (ESD) event, block ESD current to cause the ESD current to pass through one of the first and second diodes, wherein
• in response to the ESD event being a negative ESD event, the ESD current is caused to flow between the input/output node and the first reference node through the first diode, bypassing the first transistor and the second transistor, and
• in response to the ESD event being a positive ESD event, the ESD current is caused to flow between the input/output node and the second reference node through the second diode, bypassing the third transistor and the fourth transistor.

A method of fabricating a semiconductor device, the method comprising:

• forming first and second active regions over a substrate;
• forming first and second gate electrodes and a gate electrode portion in a same layer over the first and second active regions, wherein:
• the gate electrode portion is transverse to the first and second gate electrodes, and connects the first gate electrode to the second gate electrode,
• the first and second gate electrodes and the first active region configure a first transistor,
• the first and second gate electrodes and the second active region configure a second transistor, wherein the first transistor has a first body and the second transistor has a second body;
• and
• forming conductors and conductive vias over the first and second active regions and the first and second gate electrodes such that
• the first body of the first transistor is electrically connected to a first source of the first transistor by a first conductor among the conductors, the first conductor configured to receive a first reference voltage, and
• the second body and a second source of the second transistor are electrically connected to a first drain terminal of the first transistor by a second conductor among the conductors,
• wherein
• the first and second active regions are of a same semiconductor type and are physically disconnected, by a spacing, from each other over the substrate,
• the first and second gate electrodes continuously extend from the first active region, across the spacing, to the second active region,
• the method further comprises forming an input/output node, a plurality of transistors, and first and second diodes
• the plurality of transistors comprises the first and second transistors, and third and fourth transistors,
• the first body and the first source of the first transistor are directly connected to a first reference node which is configured to receive the first reference voltage, wherein:
• the first transistor and the second transistor are electrically connected in series,
• the second body of the second transistor is electrically disconnected from the first body of the first transistor,
• the first gate electrode and the second gate electrode are directly connected to a first node configured to receive a first control signal,
• the first transistor and the second transistor are of a same, first conductivity type, and
• a second drain of the second transistor is directly connected to the input/output node,
• the third transistor has a third body and a third source, wherein the third body and the third source of the third transistor are directly connected to a second reference node which is configured to receive a second reference voltage different from the first reference voltage,
• the fourth transistor has a fourth body, wherein
• the third transistor and the fourth transistor are electrically connected in series,
• the fourth body of the fourth transistor is electrically disconnected from the third body of the third transistor,
• a third gate electrode of the third transistor is directly connected to a fourth gate electrode of the fourth transistor and to a second node configured to receive a second control signal different from the first control signal,
• the third transistor and the fourth transistor are of a same, second conductivity type different from the first conductivity type, and
• a drain of the fourth transistor is directly connected to the input/output node,
• the first diode is connected between the input/output node and the first reference node,
• the second diode is connected between the input/output node and the second reference node, and
• the plurality of transistors is configured to, during an electrostatic discharge (ESD) event, block ESD current to cause the ESD current to pass through one of the first and second diodes, wherein
• in response to the ESD event being a negative ESD event, the ESD current is caused to flow between the input/output node and the first reference node through the first diode, bypassing the first transistor and the second transistor, and
• in response to the ESD event being a positive ESD event, the ESD current is caused to flow between the input/output node and the second reference node through the second diode, bypassing the third transistor and the fourth transistor.