Protection circuit and semiconductor integrated circuit device

A protection circuit for preventing an overcurrent caused by applying a supply voltage having a reverse polarity to a circuit to which power is supplied via a ground terminal and a supply terminal, the protection circuit comprising:

• a first transistor including a gate and a bulk, and being a p-type field effect transistor (FET), the first transistor being provided in a path between the supply terminal and a common node;
• a second transistor including a gate and a bulk, and being the p-type FET, the second transistor being provided in a path between the ground terminal and the common node;
• a third transistor including a bulk, and being the p-type FET, and the third transistor being provided in a path between the supply terminal and the circuit;
• a first gate drive configured to output a first drive voltage to the gate of the first transistor;
• and
• a second gate drive configured to output a second drive voltage to the gate of the second transistor,
• wherein the bulk of each of the first transistor, the second transistor, and the third transistor is in communication with the common node,
• wherein the first gate drive is configured to
• output the first drive voltage to turn the first transistor off, upon occurrence of a condition in which a voltage at the supply terminal is lower than a voltage at the ground terminal, and
• output the first drive voltage to turn the first transistor on, upon occurrence of a condition in which the voltage at the supply terminal is higher than the voltage at the ground terminal, the output first drive voltage being maintained higher than the voltage at the ground terminal, and
• wherein the second gate drive is configured to
• output the second drive voltage to turn the second transistor off, upon occurrence in a condition in which the voltage at the supply terminal is higher than the voltage at the ground terminal, and
• output the second drive voltage to turn the second transistor on, upon occurrence of a condition in which the voltage at the supply terminal is lower than the voltage at the ground terminal, the output second drive voltage being maintained higher than the voltage at the supply terminal.