Semiconductor device and manufacturing method thereof

A method, comprising:

• depositing an epitaxial stack over a substrate, the epitaxial stack comprising a first semiconductor layer, a second semiconductor layer, and alternating third semiconductor layers and fourth semiconductor layers, wherein the first and third semiconductor layers comprise a different semiconductor composition from that of the second and fourth semiconductor layers;
• patterning the epitaxial stack into a first fin and a second fin, wherein the first fin comprises a first portion of the first semiconductor layer, a first portion of the second semiconductor layer, a first subset of the third semiconductor layers and a first subset of the fourth semiconductor layers, and the second fin comprises a second portion of the first semiconductor layer, a second portion of the second semiconductor layer, a second subset of the third semiconductor layers and a second subset of the fourth semiconductor layers;
• forming a dielectric wall between the first and second fins;
• forming a first isolation structure over the substrate and having a top surface lower than a top surface of the dielectric wall, wherein the first fin is between the dielectric wall and the first isolation structure;
• forming a second isolation structure over the substrate and having a top surface lower than the top surface of the dielectric wall, wherein the second fin is between the dielectric wall and the second isolation structure, and the top surface of the first isolation structure is higher than the top surface of the second isolation structure;
• replacing the first subset of the third semiconductor layers with a first gate structure;
• and
• replacing the second portion of the second semiconductor layer and the second subset of the fourth semiconductor layers with a second gate structure.

A method, comprising:

• forming a dielectric wall on a substrate;
• forming a plurality of first semiconductor channels on a first side of the dielectric wall;
• forming a plurality of second semiconductor channels on a second side of the dielectric wall, wherein the second semiconductor channels comprise a different semiconductor composition from that of the first semiconductor channels, and the first semiconductor channels are misaligned with the second semiconductor channels in a cross-sectional view;
• forming a first isolation structure over the substrate and having a top surface lower than a top surface of the dielectric wall, wherein the first semiconductor channels are between the dielectric wall and the first isolation structure;
• forming a second isolation structure over the substrate and having a top surface lower than the top surface of the dielectric wall, wherein the second semiconductor channels are between the dielectric wall and the second isolation structure, and the top surface of the first isolation structure is higher than the top surface of the second isolation structure;
• forming a gate structure wrapping around the first semiconductor channels;
• and
• forming a second gate structure wrapping around the second semiconductor channels.