Semiconductor device structure with inner spacer layer

A semiconductor device structure, comprising:

• a substrate having a base;
• a multilayer stack over the base, wherein the multilayer stack comprises a first channel layer and a second channel layer over and spaced apart from the first channel layer;
• a gate stack over the substrate, wherein the gate stack wraps around the multilayer stack;
• an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base;
• a bottom spacer over the base and covering a first sidewall of the first channel layer, wherein a portion of the inner spacer layer is located between the bottom spacer and a side edge of the first channel layer;
• and
• a source/drain structure over the bottom spacer and connected to the second channel layer, wherein the source/drain structure is electrically insulated from the first channel layer.

A semiconductor device structure, comprising:

• a substrate;
• a multilayer stack over the substrate, wherein the multilayer stack comprises a first channel layer and a second channel layer over and spaced apart from the first channel layer;
• a gate stack over the substrate, wherein the gate stack wraps around the multilayer stack;
• an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the substrate and covering a sidewall of the first channel layer, wherein the inner spacer layer has a concave top surface facing away from the substrate, and the inner spacer layer extends upwards along a side edge of the first channel layer;
• and
• a source/drain structure over the inner spacer layer and connected to the second channel layer, wherein the source/drain structure is electrically insulated from the first channel layer.