High voltage transistor with a field plate

An apparatus, comprising:

• a transistor formed on a semiconductor substrate, the transistor comprising:
• a transistor gate and an extended drain between the transistor gate and a transistor drain contact;
• a transistor source contact coupled to a source contact probe pad;
• a first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack covering the semiconductor substrate and the transistor gate;
• a source field plate on the first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad;
• the source field plate capacitively coupled through the first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack to a first portion of the extended drain;
• a gate field plate over the first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack;
• the gate field plate capacitively coupled through the first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack to a second portion of the extended drain that is between the transistor gate and the first portion of the extended drain;
• and
• wherein the gate field plate couples to the transistor gate in an opening through the pre-metal dielectric layer.

An apparatus, comprising:

• a silicon drain extended metal oxide semiconductor (DEMOS) transistor formed on a semiconductor substrate, the transistor comprising:
• a transistor gate and an extended drain between the transistor gate and a transistor drain contact;
• a transistor source contact coupled to a source contact probe pad;
• a first dielectric layer covering the semiconductor substrate and the transistor gate;
• a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad;
• and
• the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

An apparatus, comprising:

• a transistor formed on a semiconductor substrate, the transistor comprising:
• a transistor gate and an extended drain between the transistor gate and a transistor drain contact;
• a transistor source contact coupled to a source contact probe pad;
• a first dielectric layer covering the semiconductor substrate and the transistor gate;
• a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad;
• the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain;
• and
• wherein the source field plate of the transistor further comprises:
• a first source field plate capacitively coupled through a first inter-metallic dielectric layer/pre-metal dielectric layer dielectric stack to the first portion of the extended drain adjacent to the transistor gate;
• the first source field plate coupled to a first source field plate probe pad;
• a second source field plate capacitively coupled through a second inter-metal dielectric layer/first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack to a third portion of the extended drain between the first portion of the extended drain and the transistor drain contact;
• and
• the second source field plate coupled to a second source field plate probe pad.

An apparatus, comprising:

• a transistor formed on a semiconductor substrate having a transistor gate and an extended drain between the transistor gate and a transistor drain contact, the transistor further comprising:
• a transistor source contact;
• a pre-metal dielectric layer covering a portion of the semiconductor substrate and the transistor gate;
• a gate field plate over the pre-metal dielectric layer and overlying a portion of the transistor gate and capacitively coupled through the pre-metal dielectric layer to a first portion of the extended drain adjacent to the transistor gate;
• a first inter-metal dielectric layer covering the pre-metal dielectric layer and the gate field plate;
• a source field plate over the first inter-metal dielectric layer;
• the source field plate overlying an end of the gate field plate and overlying a second portion of the extended drain between the first portion of the extended drain and the transistor drain contact;
• the source field plate capacitively coupled to the second portion of the extended drain through a dielectric stack of the first inter-metal dielectric layer/pre-metal dielectric layer;
• the transistor source contact coupled to a transistor source probe pad;
• and
• the source field plate coupled to a source field plate probe pad.

An apparatus, comprising:

• a transistor formed on a semiconductor substrate, the transistor comprising:
• a transistor gate and an extended drain between the transistor gate and a transistor drain contact;
• a transistor source contact coupled to a source contact probe pad;
• a first dielectric layer covering the semiconductor substrate and the transistor gate;
• a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad;
• the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain;
• and
• a mold compound covering a portion of the transistor including the extended drain and the substrate.