Semiconductor device

A semiconductor device comprising:

• a substrate;
• an active pattern which extends in a first horizontal direction on the substrate;
• a plurality of nanosheets spaced apart from each other in a vertical direction and extending in the first horizontal direction on the active pattern;
• a gate electrode which extends in a second horizontal direction different from the first horizontal direction on the substrate and surrounds each of the plurality of nanosheets;
• a field insulating layer on the substrate which surrounds side walls of the active pattern;
• an interlayer insulating layer on the field insulating layer;
• a source/drain region on at least one side of the gate electrode on the active pattern which comprises a capping layer that comprises side walls adjacent to the interlayer insulating layer;
• a source/drain contact which is electrically connected to the source/drain region and is on the source/drain region;
• and
• a silicide layer between the source/drain region and the source/drain contact wherein the silicide layer comprises a first layer along an inner surface of the source/drain region and a second layer disposed between the first layer and the source/drain contact which extends along side walls of the capping layer to an upper surface of the source/drain region,
• wherein:
• the first layer and the second layer comprise different materials from each other,
• the capping layer comprises silicon that is not doped with an impurity, and
• an uppermost surface of the silicide layer is coplanar with an uppermost surface of the capping layer.

A semiconductor device comprising:

• a substrate having a first region and a second region;
• a first active pattern which extends in a first horizontal direction on the first region of the substrate;
• a first plurality of nanosheets spaced apart from each other in a vertical direction and extending in the first horizontal direction on the first active pattern;
• a first gate electrode which extends in a second horizontal direction different from the first horizontal direction on the first region of the substrate and surrounds each of the plurality of nanosheets;
• a field insulating layer on the substrate which surrounds side walls of the first active pattern;
• an interlayer insulating layer on the field insulating layer;
• a first source/drain region on at least one side of the first gate electrode on the first active pattern which comprises a first doping layer on the first active pattern, a second doping layer on the first doping layer, and a first capping layer that comprises side walls adjacent to the interlayer insulating layer;
• a first source/drain contact which is electrically connected to the first source/drain region and is on the first source/drain region;
• and
• a first silicide layer between the first source/drain region and the first source/drain contact wherein the first silicide layer comprises a first layer along a surface of the second doping layer, a second layer extending to an upper surface of the first source/drain region along side walls of the first capping layer, and a third layer between the first layer and the first source/drain contact and between the second layer and the first source/drain contact,
• wherein one or more of the first layer, the second layer and the third layer comprise at least one different material from one or more of the other layers,
• the first capping layer comprises silicon that is not doped with an impurity, and
• the first capping layer extends from an upper surface of the field insulating layer to the upper surface of the first source/drain region along side walls of the first silicide layer.