Semiconductor devices with embedded ferroelectric field effect transistors

A device, comprising:

• a substrate;
• gate stacks and source/drain (S/D) features over the substrate;
• S/D contacts over the S/D features;
• an S/D via landing on one of the S/D contacts, wherein the S/D via is above the one of the S/D contacts;
• a ferroelectric (FE) stack landing on the S/D via, wherein the FE stack includes an FE feature and a top electrode over the FE feature;
• and
• an S/D metal line over and electrically connected to the FE stack.

A device, comprising:

• a substrate;
• gate stacks and source/drain (S/D) features over the substrate;
• a gate via landing on one of the gate stacks, wherein the gate via is above the one of the gate stacks, wherein the gate via penetrates through one or more dielectric layers to land on the one of the gate stacks;
• a ferroelectric (FE) stack landing on the gate via, wherein the FE stack includes an FE feature and a top electrode over the FE feature;
• and
• a gate metal line over and electrically connected to the FE stack.