US 12,604,489 B2 · Semiconductor devices

Abstract

A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. Each of the lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other of the tensile stress and the compressive stress.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate;
a plurality of lower electrodes on the substrate;
a dielectric layer covering the plurality of lower electrodes;
and
an upper electrode covering the dielectric layer,
wherein each of the plurality of lower electrodes includes:
a first electrode layer having a cylindrical shape,
a first insertion layer on the first electrode layer and having a cylindrical shape, and
a second electrode layer on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer,
wherein at least one of the first electrode layer and the second electrode layer has a first stress,
wherein the first insertion layer has a second stress different from the first stress,
wherein the first stress is one of a tensile stress and a compressive stress, and
wherein the second stress is the other of the tensile stress and the compressive stress.

10 more elements

A semiconductor device, comprising:

an isolation layer on a substrate, the isolation layer defining active regions;
gate electrodes crossing the active regions and extending into the isolation layer;
first impurity regions and second impurity regions in the active regions on opposite sides adjacent to the gate electrodes;
bit lines on the gate electrodes and the active regions, the bit lines being electrically connected to the first impurity regions;
conductive patterns on side surfaces of the bit lines and electrically connected to the second impurity regions;
a plurality of lower electrodes extending vertically on the conductive patterns and electrically connected to each of the conductive patterns;
at least one supporter layer contacting a side surface of each of the plurality of lower electrodes;
a dielectric layer covering the plurality of lower electrodes and the at least one supporter layer;
and
an upper electrode covering the dielectric layer,
wherein each of the plurality of lower electrodes includes:
a first electrode layer having a cylindrical shape,
an insertion layer on an internal surface of the first electrode layer, having a cylindrical shape, and including a metal oxide, and
a second electrode layer on an internal surface of the insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the insertion layer,
wherein the insertion layer is spaced apart from the dielectric layer, and
wherein an upper end of the insertion layer and an upper end of the first electrode layer are in contact with the second electrode layer.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor devices

Life of this patent

Semiconductor devices

Life of this patent

Abstract

Claims20