US 12,604,481 B2Granted

IC's with multple levels of embedded memory

AssigneeIntel Corporation

InventorsWilfred Gomes, Abhishek Anil Sharma, Uygar Avci

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Abstract

Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

Claims14

Dependent claims

An integrated circuit (IC) die, comprising:

first field effect transistors (FETs) with monocrystalline channel material;
and
an embedded memory array structure coupled to the first FETs, wherein the embedded memory array structure comprises:
a first array level on a front side of the first FETs, the first array level comprising capacitors and thin film transistors (TFTs) coupled thereto, wherein each of the capacitors in the first array level comprises a first conductor and a second conductor with a ferroelectric material therebetween;
and
a second array level on a back side of the first FETs, the second array level comprising capacitors and TFTs coupled thereto, in a vertical stack with the first array level, and with the first FETs between the first array level and the second array level, wherein each of the capacitors in the second array level comprises a first conductor and a second conductor with the ferroelectric material therebetween.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/558,446Filed 21 Dec 2021
Published: US 2023/0197654 A122 Jun 2023
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10B 53/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the three-dimensional [3D] arrangements, e.g. with…
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10B 53/40
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the peripheral circuit region
H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by

Family

US 2023/0197654 A1Pre-grant publication · published 22 Jun 2023
US 12,604,481 B2This patent

From the US filing history. Foreign family members aren’t listed.

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