US 12,604,479 B2Granted

Two transistor capacitorless memory cell with stacked thin-film transistors

AssigneeIntel Corporation

InventorsNoriyuki Sato, Abhishek A. Sharma, Van H. Le, Hui Jae Yoo

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Abstract

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S/D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S/D terminals and two gate terminals.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a support structure;
and
a memory cell over the support structure, the memory cell including a first transistor and a second transistor,
wherein:
a first channel material of the first transistor is in a first layer over the support structure,
a second channel material of the second transistor is in a second layer over the support structure, where the first layer is between the support structure and the second layer,
the second transistor includes:
a first gate stack, coupled to a portion of a first face of the second channel material of the second transistor, and
a second gate stack, coupled to a portion of a second face of the second channel material of the second transistor, where the second face is opposite the first face and is further away from the support structure than the second face,
each of the first transistor and the second transistor includes a source region and a drain region,
a first one of the source region and the drain region of the first transistor is coupled to the first gate stack of the second transistor,
a second one of the source region and the drain region of the first transistor is coupled to a write bit-line (WBL),
a first one of the source region and the drain region of the second transistor is coupled to a read bit-line (RBL), and
a second one of the source region and the drain region of the second transistor is coupled to a read word-line (RWL).

11 more elements

An integrated circuit (IC) device, comprising:

a support structure;
and
a memory cell over the support structure, the memory cell including a first transistor and a second transistor,
wherein:
a first channel material of the first transistor is in a first layer over the support structure and includes a thin-film semiconductor material,
a second channel material of the second transistor is in a second layer over the support structure and includes a substantially single-crystalline semiconductor material,
the first layer is between the support structure and the second layer,
each of the first transistor and the second transistor includes a source region and a drain region,
a first one of the source region and the drain region of the first transistor is coupled to a gate stack of the second transistor,
a second one of the source region and the drain region of the first transistor is coupled to a first control line,
a first one of the source region and the drain region of the second transistor is coupled to a second control line, and
a second one of the source region and the drain region of the second transistor is coupled to a third control line.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/471,295Filed 10 Sep 2021
Published: US 2023/0084611 A116 Mar 2023
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 12/00
Dynamic random access memory [dram] devices
H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
H10D 30/0415
Of FETs having insulated gates [IGFET]: of FETs having ferroelectric gate insulators
H10D 30/701
Insulated-gate field-effect transistors [IGFET]: iGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs

Family

US 2023/0084611 A1Pre-grant publication · published 16 Mar 2023
US 12,604,479 B2This patent

From the US filing history. Foreign family members aren’t listed.

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