Memory structure and manufacturing method thereof

A memory structure, comprising:

• a substrate;
• a first doped region located in the substrate;
• a second doped region located in the substrate;
• a first gate located on the first doped region;
• a second gate located on the second doped region;
• a first charge storage structure located between the first gate and the first doped region and comprising:
• a first tunneling dielectric layer located on the substrate;
• a first dielectric layer located on the first tunneling dielectric layer;
• and
• a first charge storage layer located between the first dielectric layer and the first tunneling dielectric layer;
• a second charge storage structure located between the second gate and the second doped region and comprising:
• a second tunneling dielectric layer located on the substrate;
• a second dielectric layer located on the second tunneling dielectric layer;
• and
• a second charge storage layer located between the second dielectric layer and the second tunneling dielectric layer, wherein
• a thickness of the second tunneling dielectric layer is greater than a thickness of the first tunneling dielectric layer;
• and
• an amorphous region located in the substrate above the second doped region, wherein the amorphous region is adjacent to a top surface of the substrate.