Semiconductor device including stack structure and trenches

A semiconductor device comprising:

• a substrate;
• a stack on the substrate;
• a plurality of pillars penetrating through the stack and contacting the substrate;
• a first trench penetrating through at least a portion of the stack;
• a second trench through the stack and adjacent to the first trench;
• first bit plugs;
• second bit plugs;
• and
• a bit line,
• wherein the stack includes insulating layers and conductive layers alternately stacked,
• wherein the conductive layers include:
• a lowermost conductive layer among the conductive layers;
• a first conductive layer on the lowermost conductive layer;
• and
• second conductive layers spaced apart from each other in a vertical direction and on the first conductive layer,
• wherein the first conductive layer has a first lateral end in a first direction,
• wherein the lowermost conductive layer has a second lateral end in the first direction,
• wherein the first direction is parallel to an upper surface of the substrate and is oriented from the second trench toward the first trench,
• wherein a first distance between the second trench and the first lateral end is different from a second distance between the second trench and the second lateral end,
• wherein a lowermost end of the first trench is at a different level from a lowermost end of the second trench,
• wherein each of the plurality of pillars includes an information storage pattern and a semiconductor pattern contacting the substrate,
• wherein with respect to the substrate, the lowermost end of the first trench and the lowermost end of the second trench are at a higher level than a lower surface of the substrate,
• wherein the plurality of pillars include cell pillars connected to the first bit plugs and dummy pillars not connected to the first bit plugs,
• wherein the bit line vertically overlaps the cell pillars, the dummy pillars, the first trench, and the second trench,
• wherein the first bit plugs are between the bit line and the cell pillars,
• wherein the second bit plugs are connected to the bit line, and
• wherein with respect to the substrate, the second bit plugs are at a higher level than the first bit plugs and are at a lower level than the bit line.