Semiconductor structure having word line and manufacturing method thereof

A manufacturing method of a semiconductor structure, comprising:

• forming a capacitor structure in a first dielectric layer and a second dielectric layer that is located on the first dielectric layer, wherein the capacitor structure comprises a semiconductor material;
• forming a source region on a top of the capacitor structure;
• forming a third dielectric layer and a word line on the second dielectric layer, wherein the word line is located in the third dielectric layer and extends across the capacitor structure, wherein a portion of the third dielectric layer is between the word line and the capacitor structure;
• forming a channel hole in the third dielectric layer to expose the word line, wherein said portion of the third dielectric layer, the word line, and the capacitor structure are aligned with each other, and the source region is between the top of the capacitor structure and a bottom of said portion of the third dielectric layer, and a top of said portion of the third dielectric layer and the bottom of said portion of the third dielectric layer are respectively in direct contact with the a bottom of the word line and a top of the source region, and an orthogonal projection of the entire said portion of the third dielectric layer and an orthogonal projection of the entire word line on the top of the capacitor structure completely overlap with each other and are only located on the semiconductor material of the capacitor structure;
• forming a first portion and a second portion of a gate dielectric respectively on a sidewall of the word line and an inner sidewall of the third dielectric layer;
• and
• forming a channel structure in the channel hole of the third dielectric layer, wherein the channel structure surrounds the word line and said portion of the third dielectric layer.