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US 12,604,461 B2Granted
Dynamic random access memory
AssigneeNanya Technology Corporation
InventorsChiang-Lin Shih, Yu-Ting Lin
Life of this patent
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Abstract
A dynamic random access memory includes an array region, a bottom capacitor array located in the array region, and a top capacitor array located in the array region and located on the bottom capacitor array. The bottom capacitor array is single-sided capacitor array. The top capacitor is a double-sided capacitor array.
Claims14
A dynamic random access memory, comprising:
- an array region;
- a bottom capacitor array located in the array region, wherein the bottom capacitor array is single-sided capacitor array;
- a top capacitor array located in the array region and located on the bottom capacitor array, wherein the top capacitor array is a double-sided capacitor array, the top capacitor array comprises a plurality of top capacitor structures, and each of the top capacitor structures comprises:
- a top electrode;
- a second dielectric layer surrounding the top electrode partially;
- and
- a bottom electrode surrounding the second dielectric layer partially, and the bottom electrode of each of the top capacitor structures has a U-shape;
- and
- a plurality of landing pads located between the top capacitor array and the bottom capacitor array, wherein each of the top capacitor structures comprises an end facing the landing pads, and a width of the end of each one of the top capacitor structures is smaller than an average width of each one of the landing pads.
6 more elements
A dynamic random access memory, comprising:
- an array region;
- a bottom capacitor array located in the array region, wherein the bottom capacitor array comprises a plurality of bottom capacitor structures, and each of the bottom capacitor structures comprises:
- a top electrode;
- a dielectric layer surrounded by the top electrode;
- and
- a bottom electrode surrounded by the dielectric layer and the top electrode;
- a top capacitor array located in the array region and located on the bottom capacitor array, the top capacitor array comprises a plurality of top capacitor structures, and each of the top capacitor structures comprises:
- a top electrode;
- a second dielectric layer surrounding the top electrode partially;
- and
- a bottom electrode surrounding the second dielectric layer partially, and the bottom electrode of each of the top capacitor structures has a U-shape;
- and
- a plurality of landing pads located between the top capacitor array and the bottom capacitor array, wherein each of the top capacitor structures comprises an end facing the landing pads, and a ratio derived from dividing a width of the end of each one of the top capacitor structures by an average width of each one of the landing pad is in a range from about 0.5 to 0.55.
10 more elements
Dependencies are inferred from the claim text.