Semiconductor memory device

A semiconductor memory device, comprising:

• a substrate comprising at least an array region;
• a peripheral region bordering an edge of the array region;
• a plurality of contact pads disposed on the array region;
• and
• a capacitor array structure disposed on the array region, and comprising:
• a plurality of capacitors respectively disposed on the contact pads;
• and
• a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the upper portions of the capacitors near the edge of the array region are tilted and have misalignments to the contact pads, wherein distances of the misalignments are larger as the capacitors closer to the edge of the array region.

A semiconductor memory device, comprising:

• a substrate comprising at least an array region;
• a peripheral region bordering an edge of the array region;
• a plurality of contact pads disposed on the array region;
• and
• a capacitor array structure disposed on the array region, and comprising:
• a plurality of capacitors respectively disposed on the contact pads;
• and
• a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the lower portions of the capacitors near the edge of the array region are tilted, and the upper portions of the capacitors near the edge of the array region have misalignments to the contact pads, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.

A semiconductor memory device, comprising:

• a substrate comprising at least an array region;
• a peripheral region bordering an edge of the array region;
• a plurality of contact pads disposed on the array region;
• and
• a capacitor array structure disposed on the array region, and comprising:
• a plurality of capacitors respectively disposed on the contact pads;
• and
• a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the upper portions of the capacitors near the edge of the array region are tilted and have misalignments to the contact pads, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.