US 12,604,457 B2Granted

Semiconductor memory device

AssigneeKioxia Corporation

InventorsTakafumi Masuda, Mutsumi Okajima, Nobuyoshi Saito, Keiji Ikeda

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Abstract

A semiconductor memory device comprises: a first memory layer; and a first via wiring and a second via wiring extending in a first direction, and having different positions from each other in a second direction. The first memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a first wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring and the first wiring; a first electrode electrically connected to the second transistor; and a second electrode electrically connected to the first wiring and first electrode. A length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate;
a first memory layer separated from the substrate in a first direction intersecting a surface of the substrate;
and
a first via wiring and a second via wiring that extend in the first direction, and have different positions from each other in a second direction intersecting the first direction, wherein
the first memory layer comprises:
a first transistor which is electrically connected to the first via wiring;
a memory portion which is electrically connected to the first transistor;
a first wiring which is electrically connected to the first transistor, and extends in the second direction;
a second transistor which is electrically connected to the second via wiring, and is electrically connected to the first wiring;
a first electrode which is electrically connected to the second transistor;
and
a second electrode which is electrically connected to the first wiring and the first electrode,
the first electrode includes a first conductive layer and a second conductive layer that are arranged in the first direction,
the second conductive layer includes a conductive oxide, and
a length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/459,978Filed 1 Sep 2023
Priority: JP 2022-1410935 Sep 2022
Published: US 2024/0081042 A17 Mar 2024
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/02
Manufacture or treatment: for one transistor one-capacitor [1T-1C] memory cells
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto

Family

US 2024/0081042 A1Pre-grant publication · published 7 Mar 2024
US 12,604,457 B2This patent

From the US filing history. Foreign family members aren’t listed.

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