US 12,604,454 B2Granted

Memory device

AssigneeKioxia Corporation

InventorsReiko Sumi, Takashi Inukai, Tsuneo Inaba, Takayuki Miyazaki

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Abstract

A memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

Claims18

Dependent claims

A memory device comprising:

a memory cell array including a first sub-array including a plurality of first memory cells, a second sub-array including a plurality of second memory cells, a third sub-array including a plurality of third memory cells, and a fourth sub-array including a plurality of fourth memory cells;
a first bit line coupled to the first sub-array and the second sub-array and extending in a first direction;
a second bit line arranged side by side with the first bit line in the first direction and coupled to the third sub-array and the fourth sub-array;
a third bit line arranged at a position different from the first bit line in a second direction intersecting the first direction and coupled to at least the second sub-array and the third sub-array;
a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array;
a first circuit electrically coupled to the first bit line and the second bit line;
and
a second circuit electrically coupled to the third bit line and the fourth bit line.

5 more elements

A memory device comprising:

a first chip including:
a memory cell array including a first sub-array including a plurality of first memory cells and a second sub-array including a plurality of second memory cells;
a first bit line coupled to the first sub-array and extending in a first direction;
and
a second bit line arranged side by side with the first bit line in the first direction and coupled to the second sub-array, and
a second chip including a first circuit to which the first bit line and the second bit line are electrically coupled,
wherein
the first bit line is electrically coupled to the first circuit via a first pad provided on a bonding surface of the first chip and the second chip,
the second bit line is electrically coupled to the first circuit via a second pad provided on the bonding surface, and
the first circuit is arranged between the first pad and the second pad in the first direction.

7 more elements

A memory device comprising:

a first chip including:
a memory cell array including a first sub-array including a plurality of first memory cells;
a first bit line coupled to the first sub-array and extending in a first direction;
a second bit line arranged side by side with the first bit line in a second direction intersecting the first direction;
a third bit line arranged side by side with the second bit line in the second direction;
and
a fourth bit line arranged side by side with the third bit line in the second direction, and
a second chip including:
a first circuit to which the first bit line and the second bit line are electrically coupled;
and
a second circuit to which the third bit line and the fourth bit line are electrically coupled,
wherein the first bit line is electrically coupled to the first circuit via a first pad provided on a bonding surface of the first chip and the second chip, and
the second bit line is electrically coupled to the first circuit via a second pad provided on the bonding surface,
the third bit line is electrically coupled to the second circuit via a third pad provided on the bonding surface,
the fourth bit line is electrically coupled to the second circuit via a fourth pad provided on the bonding surface,
the first pad, the first circuit, and the second pad are arranged side by side in the first direction,
the third pad, the second circuit, and the fourth pad are arranged side by side in the first direction, and
the second pad and the third pad are not adjacent to each other in the first direction.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/601,832Filed 11 Mar 2024
Priority: JP 2023-04421520 Mar 2023
Published: US 2024/0324169 A126 Sep 2024
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/485
Data lines or contacts therefor: bit line contacts
H10B 12/488
Data lines or contacts therefor: word lines

Family

US 2024/0324169 A1Pre-grant publication · published 26 Sep 2024
US 12,604,454 B2This patent

From the US filing history. Foreign family members aren’t listed.

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