Compact electrical connection that can be used to form an SRAM cell and method of making the same

A device, comprising:

• a first semiconductor active area;
• a first gate directly adjacent to the first semiconductor active area;
• a conductive contact that is electrically coupled to the first semiconductor active area;
• an expanded conductive via that overlays the conductive contact, the expanded conductive via including:
• a first conductive portion that extends in a plane from the conductive contact to the first gate;
• and
• a second conductive portion that extends downward from the first conductive portion and is directly connected to the first gate, the second conductive portion being the same material as the first conductive portion;
• a first electrical insulation layer that surrounds the expanded conductive via;
• a second semiconductor active area offset from the first semiconductor active area in a first direction;
• a first channel region formed by the first gate overlying the second semiconductor active area;
• a second gate overlying a second channel region of the first semiconductor active area, the second gate offset from the first gate in a second direction, the second direction being perpendicular to the first direction;
• and
• a first transistor that includes the first channel region, a first source region adjacent to a first side of the first channel region in the second semiconductor active area, and a first drain region adjacent to the second side of the first channel region and the first gate.

A device, comprising:

• a first semiconductor active area;
• a first gate overlapping a second semiconductor active area offset from the first semiconductor active area;
• a first channel region formed by the first gate overlying the second semiconductor active area;
• a conductive contact that is directly connected to the first semiconductor active area, the conductive contact formed of a first conductive material;
• an expanded conductive via that overlays the conductive contact and directly contacts the first gate, electrically coupling the first semiconductor active area to the first gate, the expanded conductive via including:
• a first conductive portion that extends in a plane from the conductive contact to the first gate;
• and
• a second conductive portion that extends downward from the first conductive portion and is directly connected to the first gate, the second conductive portion being the same material as the first conductive portion;
• a second gate overlying the first semiconductor active area forming a second channel region, the second gate being directly adjacent to a first drain region of the first semiconductor active area;
• a first electrical insulation layer that surrounds the expanded conductive via;
• and
• a first transistor that includes the first channel region, a source region adjacent to a first side of the first channel region in the second semiconductor active area, and a second drain region adjacent to a second side of the first channel region and the first gate.