Semiconductor circuit, imaging device, and electronic device

An imaging device, comprising:

• a pixel array part that includes a plurality of pixels, wherein
• the plurality of pixels includes a plurality of photoelectric conversion units, and
• the plurality of photoelectric conversion units is in a two-dimensional array;
• a plurality of signal lines configured to transmit a plurality of pixel signals, wherein the plurality of pixels is configured to perform photoelectric conversion on the plurality of pixel signals;
• an internal voltage generation circuit configured to generate a bias voltage;
• a sample hold circuit configured to sample the bias voltage in a first time period and hold the bias voltage in the first time period;
• a current source configured to control a current through the plurality of signal lines based on the held bias voltage;
• and
• an AD converter configured to generate, based on a result of comparison between each of the plurality of pixel signals and a reference signal, a plurality of digital signals corresponding to the plurality of pixel signals, wherein
• the plurality of pixel signals is on the plurality of signal lines, and
• the sample hold circuit includes:
• a first transistor connected to a first node, wherein the first transistor is configured to:
• transition from an on-state to an off-state;
• and
• control transmission of an input signal to the first node based on the transition of the first transistor from the on-state to the off-state;
• a second transistor configured to switch between an off-state and an on-state, wherein
• the second transistor includes a source and a drain, and
• each of the source of the second transistor and the drain of the second transistor is connected to the first node;
• and
• a third transistor configured to transition from an on-state to an off-state, wherein
• the third transistor includes a source and a drain,
• the source of the third transistor is connected to the first node,
• the drain of the third transistor is connected to a second node,
• the second node is different from the first node,
• based on the transition of the third transistor from the on-state to the off-state, the first node is one of electrically short circuit from the second node or electrically cut off from the second node,
• the switch of the second transistor between the on-state and the off-state is associated with a gate waveform of the second transistor,
• the gate waveform of the second transistor is opposite in phase to a gate waveform of the first transistor at a second time period,
• the second time period is a time period after the transition of the first transistor from the on-state to the off-state,
• the transition of the third transistor from the on-state to the off-state is at a third time period, and
• the third time period is a time period after the switch of the second transistor between the off-state and the on-state.