Method for performing image decompression with limited hardware resource, associated image processing circuit and associated electronic device

A method for performing image decompression with limited hardware resource, the method being applicable to an image processing circuit, the method comprising:

• utilizing a receiving (RX) first in first out (FIFO) buffer within the image processing circuit to receive compressed data of a predetermined image;
• utilizing a bitstream buffer within the image processing circuit to buffer a bitstream carrying the compressed data;
• utilizing a first decompressor among multiple decompressors within the image processing circuit to perform decompression, wherein utilizing the first decompressor among the multiple decompressors within the image processing circuit to perform the decompression comprises:
• utilizing an inverse quantization circuit within the first decompressor to perform inverse quantization processing according to the bitstream to generate a first processing result;
• and
• utilizing an up-sampling circuit within the first decompressor to perform up-sampling processing on the first processing result to generate a second processing result, for generating a decompressed image as a reproduced version of the predetermined image;
• wherein during generating the decompressed image according to the bitstream, the image processing circuit is arranged to prevent using any entropy decoding circuit, any quantization table, any de-zigzag circuit, and any inverse transform circuit associated with said any entropy decoding circuit, said any quantization table and said any de-zigzag circuit;
• utilizing a transmitting (TX) FIFO buffer within the image processing circuit to output data of the decompressed image;
• and
• utilizing a TX FIFO handler within the image processing circuit to temporarily store first decompressed data from at least one portion of decompressors among the multiple decompressors, and control which decompressed data in the first decompressed data is sent into the TX FIFO buffer to be second decompressed data;
• wherein the TX FIFO buffer is arranged to output the second decompressed data, wherein the second decompressed data comprises the data of the decompressed image;
• wherein any decompressor among the multiple decompressors is arranged to use multiple handshaking signals to perform handshaking with a previous stage and a subsequent stage, respectively, wherein the multiple handshaking signals comprise multiple first handshaking signals corresponding to the previous stage and multiple second handshaking signals corresponding to the subsequent stage to allow a pipeline architecture of the image processing circuit to operate correctly;
• and the image processing circuit is arranged to selectively enable at least one decompressor among the multiple decompressors for performing image decompression, wherein in the pipeline architecture, the bitstream buffer and the TX FIFO handler are located before and after the at least one decompressor, respectively, the RX FIFO buffer is located before the bitstream buffer, and the TX FIFO buffer is located after the TX FIFO handler.