Successive approximation register A/D converter

A successive approximation register A/D converter comprising:

• a capacitive array D/A converter structured to sample an input voltage, to convert control data into a threshold voltage, and to output a signal that corresponds to the input voltage and the threshold voltage;
• a comparison circuit structured to receive an output of the capacitive array D/A converter, and to perform comparison processing according to a comparison clock;
• a clock generating circuit structured to generate a successive approximation clock based on an output of the comparison circuit;
• and
• a logic circuit structured to receive a comparison signal that indicates a comparison result of the comparison circuit and the successive approximation clock, to update the control data, and to supply the comparison clock based on the successive approximation clock to the comparison circuit,
• wherein the logic circuit is structured to count the successive approximation clock and an external clock after a start of A/D conversion, to judge that operation is normal when a predetermined second number of cycles of the successive approximation clock is detected before detection of a predetermined first number of cycles of the external clock, and to judge that an abnormal state has occurred when the predetermined second number of cycles of the successive approximation clock have not been detected at a time point at which the first number of cycles of the external clock have been detected,
• wherein the logic circuit comprises:
• a first circuit structured to count the external clock after an assertion of a start signal that indicates the start of A/D conversion of the A/D converter, and to assert a first timing signal in response to detection of the first number of cycles of the external clock;
• a second circuit structured to count the successive approximation clock after the assertion of the start signal and to assert a second timing signal in response to detection of the second number of cycles of the successive approximation clock;
• and
• a judgment circuit structured to generate a fail signal that indicates the presence or absence of an abnormal state based on the first timing signal and the second timing signal.