Phase interpolator circuitry with post-distortion linearization

An electronic device comprising:

• a processor core complex configured to generate first control signals, wherein the first control signals are indicative of a first desired phase value of an output clock signal;
• and
• a clock circuit coupled to the processor core complex, comprising:
• a phase interpolator configured to generate the output clock signal based on the first control signals;
• and
• a programmable clock skew circuit coupled to the phase interpolator, wherein the programmable clock skew circuit comprises one or more programmable capacitors, the one or more programmable capacitors being configured to adjust a phase of the output clock signal based on a first delay value to compensate for at least a portion of a distortion of the output clock signal, wherein the first delay value corresponds to a first capacitance value of at least one of the one or more programmable capacitors, and wherein the programmable clock skew circuit is configured to output the output clock signal, as adjusted, with the first desired phase value.

Tangible, non-transitory, computer-readable media storing instructions that, when executed by processing circuitry, cause the processing circuitry to:

• receive a plurality of reference clock signals;
• receive control signals indicative of a desired phase value of an output clock signal;
• generate the output clock signal by combining a subset of the plurality of reference clock signals based on the control signals;
• determine a delay value based on the control signals via a lookup table comprising a plurality of delay values;
• adjust a phase value of the output clock signal based on the delay value to compensate for at least a portion of a distortion of the output clock signal;
• and
• output the output clock signal, as adjusted, with the desired phase value.