Phase lock loop filter with common mode noise rejection
AssigneeBAE Systems Information and Electronic Systems Integration Inc.
InventorNorman J. Mendoza
Life of this patent
Estimating the term…
Abstract
A circuit includes (i) an input terminal for receiving a single-ended input signal; (ii) an operational amplifier (op-amp) comprising an inverting input, a non-inverting input, and an op-amp output; (iii) a capacitor coupled between the inverting input and the op-amp output; (iv) a first resistor coupled between the inverting input and the input terminal; and (v) a second resistor coupled between the non-inverting input and the input terminal. In an example, a phase locked loop (PLL) includes the circuit, and a voltage controlled oscillator (VCO) is coupled to the output of the operational amplifier.
Claims13
A circuit comprising:
- an input terminal for receiving a single-ended input signal;
- an operational amplifier (op-amp) comprising an inverting input, a non-inverting input, and an op-amp output;
- a capacitor coupled between the inverting input and the op-amp output;
- a first resistor coupled between the inverting input and the input terminal;
- a second resistor coupled between the non-inverting input and the input terminal;
- a third resistor coupled in series with the capacitor, and between the inverting input and the op-amp output;
- wherein a first terminal of the second resistor is coupled to the input terminal and a second terminal of the second resistor is coupled to the non-inverting input, the circuit comprising:
- a bias voltage supply terminal;
- and
- a fourth resistor having first and second terminals, the first terminal of the fourth resistor coupled between the non-inverting input and the second terminal of the second resistor, and the second terminal of the fourth resistor coupled to the bias voltage supply terminal.
A method comprising:
- transmitting, by a current source, a single ended current signal;
- splitting, at an input terminal, the single ended current signal to a first current signal and a second current signal;
- transmitting the first current signal over a first resistor that is coupled between the input terminal and an inverting terminal of an operational amplifier;
- transmitting the second current signal over a second resistor that is coupled between the input terminal and a non-inverting terminal of the operational amplifier;
- generating, at an output terminal coupled to an output of the operation amplifier, an output voltage, the output of the operation amplifier coupled to the inverting terminal of the operational amplifier through a third resistor and a capacitor;
- and
- biasing the non-inverting terminal of the operational amplifier through a fourth resistor;
- wherein the third resistor and the fourth resistor each have a resistance value that are substantially equal, and wherein the first resistor and the second resistor each have a resistance value that are substantially equal.
Dependencies are inferred from the claim text.