Driver circuit of switching transistor, laser driver circuit, and controller circuit of converter

A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), comprising:

• an output line connected to a gate of the switching transistor;
• a low-side line connected to a source of the switching transistor;
• a high-side line;
• a first PMOS transistor that is connected between the high-side line and the output line and receives a P gate signal at a gate of the first PMOS transistor;
• a first NMOS transistor that is connected between the output line and the low-side line and receives a first N gate signal at a gate of the first NMOS transistor;
• a second PMOS transistor that is connected between the high-side line and the output line and receives the first N gate signal at a gate of the second PMOS transistor;
• a second NMOS transistor that is connected between the output line and the low-side line and receives the P gate signal at a gate of the second NMOS transistor;
• a third NMOS transistor that is connected between the high-side line and the output line and receives a second N gate signal at a gate of the third NMOS transistor;
• and
• a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal,
• wherein in a turn-off operation of the switching transistor, the P gate signal gradually transitions to high, and subsequently the second N gate signal transitions to low and the first N gate signal gradually transitions to high.

A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), comprising:

• an output line connected to a gate of the switching transistor;
• a low-side line connected to a source of the switching transistor;
• a high-side line;
• a first PMOS transistor that is connected between the high-side line and the output line and receives a P gate signal at a gate of the first PMOS transistor;
• a first NMOS transistor that is connected between the output line and the low-side line and receives a first N gate signal at a gate of the first NMOS transistor;
• a second PMOS transistor that is connected between the high-side line and the output line and receives the first N gate signal at a gate of the second PMOS transistor;
• a second NMOS transistor that is connected between the output line and the low-side line and receives the P gate signal at a gate of the second NMOS transistor;
• a third NMOS transistor that is connected between the high-side line and the output line and receives a second N gate signal at a gate of the third NMOS transistor;
• and
• a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal,
• wherein in a turn-on operation of the switching transistor, a voltage of the output line rises with a first slope in a first period, rises with a second slope larger than the first slope during a subsequent second period, and rises with a third slope smaller than the second slope during a subsequent third period.