Shift register unit, gate driving circuit including the shift register unit and display panel including the gate driving circuit

A display panel, comprising:

• a pixel driving circuit, comprising a P-type driving transistor, a N-type switching transistor and a P-type switching transistor, wherein a first electrode of the N-type switching transistor is coupled to a gate of the driving transistor, and a first electrode of the P-type switching transistor is coupled to a first electrode of the driving transistor;
• and
• a gate driving circuit, comprising a shift register unit,
• wherein the shift register unit comprises:
• a first shift register circuit, coupled to a signal terminal group and a first output terminal, and configured to output a first shift signal to the first output terminal in response to a signal of the signal terminal group;
• and
• a second shift register circuit, coupled with the first shift register circuit, wherein the second shift register circuit is coupled to the same signal terminal group as the first shift register circuit and a second output terminal, and is configured to output a second shift signal to the second output terminal in response to the signal of the signal terminal group;
• wherein an active level of the first shift signal and an active level of the second shift signal are logically opposite;
• wherein the signal terminal group comprises an input signal terminal, a first clock signal terminal, a second clock signal terminal, a first power terminal and a second power terminal;
• the first shift register circuit comprises:
• a first input circuit, coupled to the first power terminal, the first clock signal terminal and a first node, and configured to transmit a signal of the first power terminal to the first node in response to a signal of the first clock signal terminal;
• a second input circuit, coupled to the first power terminal, the input signal terminal and a second node, and configured to transmit the signal of the first power terminal to the second node in response to a signal of the input signal terminal;
• a first control circuit, coupled to the first node, the second node and a pull-up node, and configured to transmit a signal of the pull-up node to the first node in response to a signal of the second node, wherein the pull-up node is the first clock signal terminal or the second power terminal;
• a second control circuit, coupled to the first node, the second node, the second power terminal and the second clock signal terminal, and configured to transmit a signal of the second power terminal to the second node in response to signals of the first node and the second clock signal terminal;
• a first output circuit, coupled to the second power terminal, the first output terminal and the first node, and configured to transmit the signal of the second power terminal to the first output terminal in response to a signal of the first node;
• a second output circuit, coupled to the second clock signal terminal, the second node and the first output terminal, and configured to transmit a signal of the second clock signal terminal to the first output terminal in response to the signal of the second node;
• a first storage circuit, coupled to the first node;
• and
• a second storage circuit, coupled to the second node,
• wherein the first input circuit comprises:
• a first transistor, wherein a first electrode of the first transistor is coupled to the first power terminal, a second electrode of the first transistor is coupled to the first node, and a gate of the first transistor is coupled to the first clock signal terminal;
• the second input circuit comprises:
• a second transistor, wherein a first electrode of the second transistor is coupled to the first power terminal, a second electrode of the second transistor is coupled to the second node, and a gate of the second transistor is coupled to the input signal terminal;
• the first control circuit comprises:
• a third transistor, wherein a first electrode of the third transistor is coupled to the pull-up node, a second electrode of the third transistor is coupled to the first node, and a gate of the third transistor is coupled to the second node;
• the second control circuit comprises:
• a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the second power terminal, and a gate of the fourth transistor is coupled to the first node;
• and
• a fifth transistor, wherein a first electrode of the fifth transistor is coupled to a second electrode of the fourth transistor, a second electrode of the fifth transistor is coupled to the second node, and a gate of the fifth transistor is coupled to the second clock signal terminal;
• the first output circuit comprises:
• a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the second power terminal, a second electrode of the sixth transistor is coupled to the first output terminal, and a gate of the sixth transistor is coupled to the first node;
• the second output circuit comprises:
• a seventh transistor, wherein a first electrode of the seventh transistor is coupled to the second clock signal terminal, a second electrode of the seventh transistor is coupled to the first output terminal, and a gate of the seventh transistor is coupled to the second node;
• the first storage circuit comprises:
• a first capacitor, coupled between the second power terminal and the first node;
• and
• the second storage circuit comprises:
• a second capacitor, coupled between the second node and the first output terminal;
• wherein the first output terminal of the shift register unit in the gate driving circuit is configured to provide a gate driving signal to the P-type switching transistor, and the second output terminal of the shift register unit in the gate driving circuit is configured to provide the gate driving signal to the N-type switching transistor.

A shift register unit, comprising:

• a first shift register circuit, coupled to a signal terminal group and a first output terminal, and configured to output a first shift signal to the first output terminal in response to a signal of the signal terminal group;
• and
• a second shift register circuit, coupled with the first shift register circuit, wherein the second shift register circuit is coupled to the same signal terminal group as the first shift register circuit and a second output terminal, and is configured to output a second shift signal to the second output terminal in response to the signal of the signal terminal group;
• wherein an active level of the first shift signal and an active level of the second shift signal are logically opposite;
• wherein the signal terminal group comprises an input signal terminal, a first clock signal terminal, a second clock signal terminal, a first power terminal and a second power terminal;
• the first shift register circuit comprises:
• a first input circuit, coupled to the first power terminal, the first clock signal terminal and a first node, and configured to transmit a signal of the first power terminal to the first node in response to a signal of the first clock signal terminal;
• a second input circuit, coupled to the first clock signal terminal, the input signal terminal and a second node, and configured to transmit a signal of the input signal terminal to the second node in response to the signal of the first clock signal terminal;
• a first control circuit, coupled to the first node, the second node and the first clock signal terminal, and configured to transmit the signal of the first clock signal terminal to the first node in response to a signal of the second node;
• a second control circuit, coupled to the first node, the second node, the second power terminal and the second clock signal terminal, and configured to transmit a signal of the second power terminal to the second node in response to signals of the first node and the second clock signal terminal;
• a first output circuit, coupled to the second power terminal, the first output terminal and the first node, and configured to transmit the signal of the second power terminal to the first output terminal in response to a signal of the first node;
• a second output circuit, coupled to the second clock signal terminal, the second node and the first output terminal, and configured to transmit a signal of the second clock signal terminal to the first output terminal in response to the signal of the second node;
• a first storage circuit, coupled to the first node;
• and
• a second storage circuit, coupled to the second node;
• wherein the first input circuit comprises:
• a first transistor, wherein a first electrode of the first transistor is coupled to the first power terminal, a second electrode of the first transistor is coupled to the first node, and a gate of the first transistor is coupled to the first clock signal terminal;
• the second input circuit comprises:
• a second transistor, wherein a first electrode of the second transistor is coupled to the input signal terminal, a second electrode of the second transistor is coupled to the second node, and a gate of the second transistor is coupled to the first clock signal terminal;
• the first control circuit comprises:
• a third transistor, wherein a first electrode of the third transistor is coupled to the first clock signal terminal, a second electrode of the third transistor is coupled to the first node, and a gate of the third transistor is coupled to the second node;
• the second control circuit comprises:
• a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the second power terminal, and a gate of the fourth transistor is coupled to the first node;
• and
• a fifth transistor, wherein a first electrode of the fifth transistor is coupled to a second electrode of the fourth transistor, a second electrode of the fifth transistor is coupled to the second node, and a gate of the fifth transistor is coupled to the second clock signal terminal;
• the first output circuit comprises:
• a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the second power terminal, a second electrode of the sixth transistor is coupled to the first output terminal, and a gate of the sixth transistor is coupled to the first node;
• the second output circuit comprises:
• a seventh transistor, wherein a first electrode of the seventh transistor is coupled to the second clock signal terminal, a second electrode of the seventh transistor is coupled to the first output terminal, and a gate of the seventh transistor is coupled to the second node;
• the first storage circuit comprises:
• a first capacitor, coupled between the second power terminal and the first node;
• and
• the second storage circuit comprises:
• a second capacitor, coupled between the second node and the first output terminal.