US 12,603,137 B2 · Memory systems, operating methods, and readable storage mediums

Abstract

Examples of the present application disclose memory systems, methods of operating the same, and readable storage mediums. An example memory system includes a memory device and a memory controller coupled to the memory device. The memory controller is configured to: in response to a read command, determine a time period to which a time difference between writing and reading of data to be read corresponding to the read command belongs; determine an amount of the voltage shift according to the time period to which the time difference between the writing and reading of the data to be read belongs; and determine a read voltage for reading the data to be read based on the amount of the voltage shift and the default read voltage.

Claims20

Dependent claims

A memory system, comprising:

a memory device;
and
a memory controller coupled to the memory device and configured to:
in response to a read command, determine a time period to which a time difference between writing and reading of data to be read corresponding to the read command belongs;
determine an amount of a voltage shift according to the time period to which the time difference between the writing and reading of the data to be read belongs;
and
determine a read voltage for reading the data to be read based on the amount of the voltage shift and a default read voltage.

4 more elements

A method of operating a memory system, comprising:

in response to receiving a read command, determining a time period to which a time difference between writing and reading of data to be read corresponding to the read command belongs;
determining an amount of a voltage shift according to the time period to which the time difference between the writing and reading of the data to be read belongs;
and
determining a read voltage for reading the data to be read according to the amount of the voltage shift and a default read voltage.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/743,818Filed 14 Jun 2024

Priority

CN 202410268569.X8 Mar 2024

Published

US 2025/0285685 A111 Sep 2025

Granted

14 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits

Memory systems, operating methods, and readable storage mediums

Life of this patent

Memory systems, operating methods, and readable storage mediums

Life of this patent

Abstract

Claims20