Slow charge loss monitor for power up performance boosting
AssigneeMicron Technology, Inc.
InventorsNicola Ciocchini, Ugo Russo, Steven Michael Kientz
Life of this patent
Estimating the term…
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AssigneeMicron Technology, Inc.
InventorsNicola Ciocchini, Ugo Russo, Steven Michael Kientz
Estimating the term…
A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.
A memory sub-system comprising:
A method comprising:
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
Dependencies are inferred from the claim text.