Memory and reading, writing and erasing methods thereof

A memory, comprising:

• H memory planes arranged in parallel along a first direction, wherein each memory plane extends in a second direction, and the memory plane comprises M columns of memory strings;
• the memory strings extend in a third direction;
• the first direction, the second direction and the third direction are different;
• and H and M are integers greater than zero;
• wherein a single column of memory string comprises:
• N rows of memristive memory cells connected in sequence, wherein N is an integer greater than zero;
• N word lines, wherein a single word line is connected to corresponding rows of memristive memory cells;
• the word lines are used to receive word line voltages;
• and memristive memory cells in same rows receive a same word line voltage;
• gating transistors, wherein sources of the gating transistors are connected to memristive memory cells in first rows;
• gating lines, connected to gates of the gating transistors for receiving gating voltages, wherein all gating transistors on a memory plane receive a same gating voltage;
• bit lines, connected to drains of the gating transistors for receiving bit line voltages, wherein gating transistors in same columns on different memory planes receive a same bit line voltage;
• a common source line, wherein memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor.