Microelectronic devices including a control circuitry structure bonded to a memory array structure

A microelectronic device, comprising:

• a memory array structure comprising:
• array regions comprising memory cells, digit lines, and word lines;
• digit line exit regions alternating with the array regions in a first direction and comprising horizontal ends of the digit lines within horizontal areas thereof;
• and
• word line exit regions alternating with the array regions in a second direction and comprising horizontal ends of the word lines within horizontal areas thereof;
• a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising:
• control circuitry regions horizontally overlapping the array regions of the memory array structure;
• digit line contact sections horizontally overlapping the digit line exit regions of the memory array structure;
• word line contact sections horizontally overlapping the word line exit regions of the memory array structure;
• sense amplifier sections respectively horizontally overlapping two of the control circuitry regions neighboring one another in the first direction;
• column decoder sections horizontally neighboring the sense amplifier sections in the first direction and comprising column decoder devices;
• sub-word line driver sections respectively horizontally overlapping two other of the control circuitry regions neighboring one another in the second direction;
• and
• main word line driver sections horizontally neighboring the sub-word line driver sections in the second direction and comprising main word line driver devices.

A microelectronic device, comprising:

• a memory array structure comprising:
• array regions comprising memory cells, digit lines, and word lines;
• digit line exit regions alternating with the array regions in a first direction and comprising horizontal ends of the digit lines within horizontal areas, the digit lines comprising:
• odd digit lines;
• and
• even digit lines alternating with the odd digit lines in a second direction;
• and
• word line exit regions alternating with the array regions in a second direction and comprising horizontal ends of the word lines within horizontal areas thereof;
• a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising:
• control circuitry regions horizontally overlapping the array regions of the memory array structure;
• digit line contact sections horizontally overlapping the digit line exit regions of the memory array structure;
• word line contact sections horizontally overlapping the word line exit regions of the memory array structure;
• sense amplifier sections respectively horizontally overlapping two of the control circuitry regions neighboring one another in the first direction and one of the digit line contact sections interposed between the two of the control circuitry regions, the sense amplifier sections respectively comprising:
• odd sense amplifier devices coupled to the odd digit lines and within a horizontal area of a first of the two of the control circuitry regions;
• and
• even sense amplifier devices coupled to the even digit lines and within a horizontal area of a second of the two of the control circuitry regions;
• wherein the one of the digit line contact sections comprises:
• odd digit line routing structures extending between and coupled to the odd digit lines and the odd sense amplifier devices;
• and
• even digit line routing structures extending between and coupled to the even digit lines and the even sense amplifier devices;
• and
• sub-word line driver sections respectively horizontally overlapping two other of the control circuitry regions neighboring one another in the second direction.

A microelectronic device, comprising:

• a memory array structure comprising array regions respectively comprising memory cells, digit lines, and word lines within horizontal areas thereof;
• and
• a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising:
• control circuitry regions horizontally overlapping the array regions of the memory array structure;
• sense amplifier sections comprising sense amplifier circuitry, the sense amplifier sections respectively horizontally overlapping a corner portion of each of four of the control circuitry regions horizontally neighboring one another in a first direction and in a second direction orthogonal to the first direction;
• sub-word line driver sections comprising sub-word line driver circuitry, the sub-word line driver sections horizontally offset from sense amplifier sections and respectively horizontally overlapping a corner portion of each of an additional four of the control circuitry regions horizontally neighboring one another in the first direction and in the second direction;
• first mini-gap sections within horizontal areas of the control circuitry regions and respectively horizontally adjacent one of the sense amplifier sections in the first direction, the first mini-gap sections comprising conductive routing structures operatively associated with sense amplifier circuitry of the sense amplifier sections;
• and
• second mini-gap sections within horizontal areas of the control circuitry regions and respectively horizontally adjacent one of the sub-word line driver sections in the second direction, the second mini-gap sections comprising additional conductive routing structures operatively associated with sub-word line driver circuitry of the sub-word line driver sections.

A microelectronic device, comprising:

• a memory array structure including array regions respectively comprising, within a horizontal area thereof:
• memory cells;
• digit lines comprising even digit lines and odd digit lines horizontally alternating with the even digit lines in a second direction orthogonal to a first direction;
• and
• word lines;
• and
• a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising:
• control circuitry regions horizontally overlapping the array regions of the memory array structure;
• sense amplifier sections comprising sense amplifier circuitry, the sense amplifier sections respectively horizontally overlapping a corner portion of each of four of the control circuitry regions horizontally neighboring one another in the first direction and in the second direction, wherein:
• some of the sense amplifier sections comprise even sense amplifier sections comprising even sense amplifier devices coupled to the even digit lines;
• and
• some other of the sense amplifier sections substantially aligned with the some of the sense amplifier sections in the second direction comprise odd sense amplifier sections comprising odd sense amplifier devices coupled to the odd digit lines;
• and
• sub-word line driver sections comprising sub-word line driver circuitry, the sub-word line driver sections horizontally offset from sense amplifier sections and respectively horizontally overlapping a corner portion of each of an additional four of the control circuitry regions horizontally neighboring one another in the first direction and in the second direction.