Parallel pipe latch for memory access operations

A system comprising:

• a host device;
• a memory device coupled to the host device, the memory device comprising:
• memory;
• pipe latch circuitry;
• and
• control circuitry configured to:
• receive a memory access command to access multiple bits of electronic data stored in the memory;
• and
• responsive to receiving the memory access command to access the memory, provide one of data read from the memory as read command data or data to be written to the memory as write command data from the control circuitry to the pipe latch circuitry and to error correction code (ECC) circuitry;
• wherein the pipe latch circuitry includes multiple parallel pipe latches in a bitslice area of the memory, wherein each respective bitslice area includes one or more circuit elements that are repeated for each bit associated with the memory access command, and wherein the multiple parallel pipe latches are configured to maintain the read command data or the write command data for different sequential memory access operations transferred via a shared data path, and wherein the pipe latch circuitry is configured to:
• receive, via the shared data path, the read command data or the write command data from the control circuitry;
• operate the multiple parallel pipe latches in parallel to handle consecutive memory access commands with a fixed timing interval between commands;
• for write operations, latch the write command data while the ECC circuitry determines an error correction code;
• and
• for read operations, latch the read command data while the ECC circuitry performs an error correction operation, and maintain the read command data for a period of time of a duration longer than error calculation time of the ECC circuitry.

A method for accessing memory, the method comprising:

• receiving, at control circuitry, a memory access command to access multiple bits of electronic data stored in the memory;
• and
• responsive to receiving the memory access command to access the electronic data stored in the memory, providing, via the control circuitry, command data of the command to pipe latch circuitry and to error correction code (ECC) circuitry,
• wherein the pipe latch circuitry includes multiple parallel pipe latches in a bitslice area of the memory, wherein each respective bitslice area includes one or more circuit elements that are repeated for each bit associated with the memory access command, and wherein the multiple parallel pipe latches are configured to handle read command data and write command data for different sequential memory access operations transferred via a shared data path, and wherein the read command data comprises data read from the memory, and wherein the write command data comprises data to be written to the memory;
• receiving, at the pipe latch circuitry and from the control circuitry using a shared data path, the read command data or the write command data;
• operating the multiple parallel pipe latches in parallel to handle consecutive memory access commands with a fixed timing interval between commands;
• for write operations, latching the write command data in one or more of the parallel pipe latches of the pipe latch circuitry while the ECC circuitry determines an error correction code;
• for read operations, latching the read command data in one or more of the parallel pipe latches of the pipe latch circuitry while the ECC circuitry performs an error correction operation;
• and
• maintaining the read command data within the pipe latch circuitry for a period of time of a duration longer than error calculation time of the ECC circuitry.