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US 12,603,121 B2Granted
Memory refresh with negative voltage generator
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorPerng-Fei Yuh
Life of this patent
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Abstract
Limiting a leakage current of a memory device is provided. A sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. A reference current having a preset value is generated. The sensing current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.
Claims20
A feedback circuit comprising:
- a reference cell array connected to a memory device, wherein the reference cell array is operative to generate a sensing current that is representative of a leakage current of the memory device;
- a reference current generator operative to generate a reference current having a preset value;
- a comparator connected to the reference cell array and the reference current generator, wherein the comparator operative to compare the reference current with the sensing current and provide an enable signal based on the comparison;
- and
- a negative voltage generator connected to the comparator, wherein the negative voltage generator operative to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to a plurality of word lines of the memory device in a standby mode.
2 more elements
A memory device, comprising:
- a memory cell array comprising a matrix of a plurality of rows and a plurality of columns, wherein each row of the plurality of rows comprises a first plurality of memory cells connected to a word line of a plurality of word lines, and wherein each column of the plurality of columns comprises a second plurality of memory cells connected to a bit line of a plurality of bit lines;
- and
- a first feedback circuit operative to provide a bias voltage to the plurality of word lines of the memory cell array during a standby mode, wherein the feedback circuit comprises:
- a reference cell array connected to the memory cell array, wherein the reference cell array generates a sensing current that is representative of a leakage current of the memory cell array device,
- a comparator connected to the reference cell array, wherein the comparator compares a reference current with the sensing current and provides an enable signal based on the comparison, and
- a negative voltage generator connected to the comparator, wherein the negative voltage generator generates a bias voltage based on the enable signal,
- wherein the bias voltage is applied to the plurality of word lines of the memory cell array in a standby mode.
4 more elements
A method of limiting a leakage current of a memory device, the method comprising:
- generating, by a reference cell array connected to a memory cell array of the memory device, a sensing current that is a representative of a leakage current of the memory cell array of the memory device;
- generating, by a reference current generator, a reference current having a preset value;
- comparing, by a comparator connected to the reference cell array and the reference current generator, the sensing current with the reference current;
- generating, by the comparator based on the comparison, an enable signal;
- and
- adjusting, by a negative voltage generator connected to the comparator, a bias voltage applied to a plurality of word lines of the memory cell array based on the enable signal.
3 more elements
Dependencies are inferred from the claim text.