Static random access memory supporting a dynamically variable duration self-time delay for a single clock cycle read-modify-write operation

A circuit that is clocked by a clock signal, comprising:

• a memory array including memory cells forming a data word location accessed in response to a word line signal;
• a plurality of bit lines associated with said memory cells;
• a data sensing circuit configured to sense data on said plurality of bit lines, said sensed data corresponding to a current data word stored at the data word location;
• a data latching circuit configured to latch the sensed data for said current data word from the data sensing circuit;
• a data modification circuit configured to perform a mathematical modify operation on the current data word to generate a modified data word;
• a data writing circuit actuated in response to assertion of a data modification complete signal to apply data for the modified data word to the plurality of bit lines for writing back to the memory cells of the memory array at said data word location;
• wherein the sensing of the data on said plurality of bit lines, the latching of the sensed data, the performing of the mathematical modify operation and the writing back of the modified data word all occur within a single cycle of the clock signal;
• a delay circuit configured to delay assertion of the data modification complete signal by a delay duration that is dynamically dependent on the current data word;
• an end detect circuit configured to assert an end signal in response to detecting the latching of the sensed data for said current data word by the data latching circuit;
• and
• wherein said delay circuit applies the delay duration to the end signal to generate the data modification complete signal.

A circuit that is clocked by a clock signal, comprising:

• a memory array including memory cells forming a data word location accessed in response to a word line signal;
• a plurality of bit lines associated with said memory cells;
• a data sensing circuit configured to sense data on said plurality of bit lines, said sensed data corresponding to a current data word stored at the data word location;
• a data latching circuit configured to latch the sensed data for said current data word from the data sensing circuit;
• a data modification circuit configured to perform a mathematical modify operation on the current data word to generate a modified data word;
• a data writing circuit actuated in response to assertion of a data modification complete signal to apply data for the modified data word to the plurality of bit lines for writing back to the memory cells of the memory array at said data word location;
• wherein the sensing of the data on said plurality of bit lines, the latching of the sensed data, the performing of the mathematical modify operation and the writing back of the modified data word all occur within a single cycle of the clock signal;
• and
• a delay circuit configured to delay assertion of the data modification complete signal by a delay duration that is dynamically dependent on the current data word;
• wherein the data modification circuit comprises a series of adder circuits configured to receive the current data word from the data latching circuit and perform the mathematical modify operation;
• wherein the delay circuit comprises:
• a series of dummy adder circuits configured to perform a dummy mathematical modify operation;
• carry comparison circuitry configured to perform a bit-by-bit comparison of carry outputs of the adder circuits and dummy adder circuits;
• and
• a logic circuit configured to assert the data modification complete signal in response to the bit-by-bit comparison performed by the carry comparison circuitry.

A circuit that is clocked by a clock signal, comprising:

• a memory array including memory cells forming a data word location accessed in response to a word line signal;
• a plurality of bit lines associated with said memory cells;
• a data sensing circuit configured to sense data on said plurality of bit lines, said sensed data corresponding to a current data word stored at the data word location;
• a data latching circuit configured to latch the sensed data for said current data word from the data sensing circuit;
• a data modification circuit configured to perform a mathematical modify operation on the current data word to generate a modified data word;
• a data writing circuit actuated in response to assertion of a data modification complete signal to apply data for the modified data word to the plurality of bit lines for writing back to the memory cells of the memory array at said data word location;
• wherein the sensing of the data on said plurality of bit lines, the latching of the sensed data, the performing of the mathematical modify operation and the writing back of the modified data word all occur within a single cycle of the clock signal;
• a delay circuit configured to delay assertion of the data modification complete signal by a delay duration that is dynamically dependent on the current data word;
• and
• a row decoder circuit configured to decode a memory address identifying said data word location and assert said word line signal for a variable self-time delay dependent on the delay duration.

A circuit, comprising:

• a memory array including memory cells forming a data word location accessed in response to a word line signal;
• a plurality of bit lines associated with said memory cells;
• and
• an input/output circuit for each bit line, comprising:
• a sensing circuit configured to sense and latch data on a bit line;
• an adder circuit configured to perform an addition operation, said adder circuit having a first input coupled to receive latched data from the sensing circuit, a second input coupled to receive data from the adder circuit of the input/output circuit for a lower significance bit line, a sum output, and a carry output coupled to supply data to the second input of the adder circuit of the input/output circuit for a higher significance bit line;
• a carry comparison logic gate configured to compare a logic state of the carry output of the adder circuit to a fixed logic state;
• and
• a data write circuit configured to write the sum output of the adder circuit to the bit line in response to assertion of a data modification complete signal;
• and
• a combination logic gate having inputs coupled to an output of each carry comparison logic gate and an output producing the data modification complete signal.