Shift register unit, gate driving circuit and display panel with pull-up voltage stabilizing circuits

A shift register unit, comprising:

• a shift register circuit, wherein
• the shift register circuit comprises:
• a display input circuit connected to a display signal input terminal and a pull-up node, and configured to write an active level signal to the pull-up node in response to an active level signal from the display signal input terminal;
• and
• at least two driving output circuits for sequentially outputting display driving pulses, wherein each driving output circuit is connected to the pull-up node, a driving clock signal input terminal and a driving signal output terminal, and is configured to write a signal from the driving clock signal input terminal to the driving signal output terminal in response to an active level signal at the pull-up node;
• the shift register circuit further comprises both a first pull-up voltage stabilizing circuit and a second pull-up voltage stabilizing circuit;
• the first pull-up voltage stabilizing circuit is connected to the pull-up node and at least configured to maintain a voltage at the pull-up node unchanged during a period in which a first driving output circuit of the at least two driving output circuits outputs the display driving pulse;
• and
• the second pull-up voltage stabilizing circuit is connected to the pull-up node and at least configured to maintain the voltage at the pull-up node unchanged during a period in which a last driving output circuit of the at least two driving output circuits outputs the display driving pulse;
• the first pull-up voltage stabilizing circuit comprises at least one first voltage stabilizing sub-circuit, each of which comprises a fifty-first transistor, a sixty-first transistor and a second capacitor, and a second electrode of the fifty-first transistor, a first electrode of the sixty-first transistor and a second terminal of the second capacitor are electrically connected together;
• the second pull-up voltage stabilizing circuit comprises at least one second voltage stabilizing sub-circuit, each of which comprises a fifty-second transistor, a sixty-second transistor and a third capacitor, and a second electrode of the fifty-second transistor, a first electrode of the sixty-second transistor and a second terminal of the third capacitor are electrically connected together;
• the driving output circuit comprises a driving output sub-circuit, which comprises a fifth transistor, a seventeenth transistor and a first capacitor, and a second electrode of the fifth transistor, a first electrode of the seventeenth transistor and a second terminal of the first capacitor are electrically connected together,
• a control electrode of the fifty-first transistor, a control node of the fifth transistor, a control electrode of the fifty-second transistor, a first terminal of the first capacitor, a first terminal of the second capacitor and a first terminal of the third capacitor are all electrically connected to the pull-up node;
• a control electrode of the sixty-first transistor, a control electrode of the sixty-second transistor, and a control electrode of the seventeenth transistor are electrically connected together;
• a second electrode of the sixty-first transistor, a second electrode of the sixty-second transistor, and a second electrode of the seventeenth transistor are all electrically connected to a fourth power supply terminal;
• and
• the first capacitor, the second capacitor and the third capacitor have a same capacitance.