Driving circuit and display device

A driving circuit, having a plurality of stages and supplying a drive signal to scanning signal lines in a scanning signal line group in response to supplying a first clock signal and a second clock signal, the driving circuit comprising:

• a first unit circuit forming one of the stages and outputting the drive signal to one of the scanning signal lines in the scanning signal line group,
• wherein the first unit circuit includes:
• a node;
• a first transistor that outputs the drive signal to the scanning signal line, with a gate electrode of the first transistor connected to the node, a source electrode of the first transistor supplied with the first clock signal and a drain electrode of the first transistor connected to the scanning signal line;
• a second transistor that is supplied with a set signal for the first unit circuit, with a gate electrode of the second transistor supplied with the set signal and a drain electrode of the second transistor connected to the node;
• a third transistor that is supplied with a reset signal for the first unit circuit, with a gate electrode of the third transistor supplied with the reset signal and a drain electrode of the third transistor connected to the node, wherein the second clock signal has a phase different from a phase of the first clock signal, and has a voltage remaining at a high level for a time period from a start point to an end point, the start point being prior to a time point of supplying the reset signal and within a time period throughout which a potential of the node is higher than a gate-on voltage of the third transistor and the end point falling between the time point of supplying the reset signal and a time point of stopping supplying the reset signal, and
• wherein the third transistor is configured to receive the second clock signal at a source electrode of the third transistor.