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US 12,602,575 B2Granted
Performing processing-in-memory operations related to pre-synaptic spike signals, and related methods and systems
AssigneeMicron Technology, Inc.
InventorsDmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
Life of this patent
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Abstract
Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.
Claims20
A system, comprising:
- a memory array comprising a number of memory cells at intersections of a number of word lines and a number of bit lines;
- and
- circuitry coupled to the memory array and configured to:
- generate, in response to a first signal driven on a word line of the number of word lines, a second signal with a voltage, current, or timing characteristic, or combination thereof that either increases or decreases a conductance of a memory cell of the number of memory cells on a bit line of the number of bit lines;
- and
- integrate current on the bit line intersecting the word line.
3 more elements
A method, comprising:
- generating a first signal with a voltage, current, or timing characteristic, or combination thereof that modifies a conductance of a memory cell in a long-term potentiation (LTP) window of a spike timing dependent plasticity (STDP) characteristic;
- transmitting the first signal to a bit line coupled to the memory cell;
- and
- in response to generation of a spike signal of a neuron driven on the bit line, transmitting a feedback signal to each memory cell on the bit line, wherein the feedback signal is a decaying bias.
1 more element
An electronic system, comprising:
- at least one input device;
- at least one output device;
- at least one processor device operably coupled to the input device and the output device;
- and
- at least one memory device operably coupled to the at least one processor device and comprising:
- a number of memory cells;
- and
- circuitry configured to:
- generate, in response to a first signal driven on a word line of the number of word lines, a second a signal with a voltage, current, or timing characteristic, or combination thereof that modifies a conductance of a memory cell of the number of memory cells;
- transmit the second signal to a bit line coupled to the memory cell;
- and
- transmit, in response to a spike signal of a neuron driven on the bit line, a decaying bias feedback signal to each memory cell on the bit line.
9 more elements
Dependencies are inferred from the claim text.