Automated transistor-level placement for design of integrated circuits

A computer-implemented method for designing an integrated circuit using transistor placement optimization, the method comprising:

• receiving, by a computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;
• determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;
• using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;
• using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;
• using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design;
• and
• storing, by the computing system, the completed design in a layout data store;
• wherein using the objective function to generate the rough placement having globally optimized locations and orientations for the plurality of transistors includes:
• using an analytic technique to optimize locations of the plurality of transistors in a continuous coordinate space;
• and
• creating a preliminary discrete layout by converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in a discrete coordinate space.

A non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by one or more processors of a computing system, cause the computing system to perform actions for designing an integrated circuit using transistor placement optimization, the actions comprising:

• receiving, by the computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;
• determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;
• using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;
• using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;
• using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design;
• and
• storing, by the computing system, the completed design in a layout data store.

A non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by one or more processors of a computing system, cause the computing system to perform actions for designing an integrated circuit using transistor placement optimization, the actions comprising:

• receiving, by the computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;
• determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;
• using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;
• using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;
• using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design;
• and
• storing, by the computing system, the completed design in a layout data store
• wherein using the objective function to generate the rough placement having globally optimized locations and orientations for the plurality of transistors includes:
• using an analytic technique to optimize locations of the plurality of transistors in a continuous coordinate space;
• and
• creating a preliminary discrete layout by converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in a discrete coordinate space.