Multi-chip module (MCM) with multi-port unified memory
AssigneeEliyan Corporation
InventorRamin Farjadrad
Life of this patent
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Abstract
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.
Claims17
An integrated circuit (IC) base die to couple to a stack of memory die, the IC base die comprising:
- a first port comprising a die-to-die (D2D) interface to couple to an IC device, the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
- a second port comprising a memory interface to access a memory other than the stack of memory die;
- and
- memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.
A memory chiplet to couple to a package substrate of a system-in-package (SiP), the memory chiplet comprising:
- a stack of memory die;
- and
- an integrated circuit (IC) base die coupled to the stack of memory die, the IC base die comprising
- a first port comprising a die-to-die (D2D) interface to couple to an IC device, the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
- a second port comprising a memory interface to access a memory other than the stack of memory die;
- and
- memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.
A system-in-package (SiP) to couple to a base substrate, the SiP comprising:
- a package substrate that is separate from the base substrate;
- an integrated circuit device coupled to the package substrate;
- a memory chiplet coupled to the package substrate, the memory chiplet comprising
- a stack of memory die;
- and
- an integrated circuit (IC) base die coupled to the stack of memory die, the IC base die comprising
- a first port comprising a die-to-die (D2D) interface to couple to an IC device the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
- a second port comprising a memory interface to access a memory other than the stack of memory die;
- and
- memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.
Dependencies are inferred from the claim text.