Apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture

An apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to:

• determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions;
• determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions;
• and
• generate logic to be performed by one or more of the plurality of units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency,
• wherein the plurality of units of computing circuitry of the computing architecture comprises a plurality of logic tiles of a field-programmable gate array, with the plurality of logic tiles being operable at different clock frequencies.