Secure debugging

A method for a secure debugging of a processing unit of an integrated circuit, the method comprising:

• receiving a debugging initiation request based on a trigger event;
• determining a debugging enablement, the debugging enablement allowing the secure debugging of the processing unit after the debugging initiation request is received;
• preparing at least a part of the integrated circuit for the secure debugging responsive to the determination of the debugging enablement, wherein the preparing comprises validating that programs executed by the processing unit and not related to the secure debugging are terminated prior to the secure debugging;
• allowing, by an access control unit of the integrated circuit, the secure debugging of the processing unit responsive to completion of the preparation and upon receiving the debug request via a debug port of the integrated circuit;
• and
• executing the secure debugging of the processing unit responsive to the allowance of the secure debugging.

At least one non-transitory machine-readable storage medium, comprising a plurality of instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the computer-controlled device to:

• receive a debugging initiation request based on a trigger event;
• determine a debugging enablement, the debugging enablement allowing the secure debugging of the processing unit after the debugging initiation request is received;
• prepare at least a part of the integrated circuit for the secure debugging responsive to the determination of the debugging enablement, wherein the preparing comprises validating that programs executed by the processing unit and not related to the secure debugging are terminated prior to the secure debugging;
• allow, by an access control unit of the integrated circuit, the secure debugging of the processing unit responsive to completion of the preparation and upon receiving the debug request via a debug port of the integrated circuit;
• and
• execute the secure debugging of the processing unit responsive to the allowance of the secure debugging.