Memory expander and computing system including the same

A computing system comprising:

• a host device;
• and
• a first compute express link (CXL) memory device connected to the host device,
• wherein the first CXL memory device includes:
• a CXL interface connected to the host device and configured to communicate with the host device;
• a first memory sub-module connected to the CXL interface;
• a second memory sub-module connected to the CXL interface;
• a first power management integrated circuit connected to a first power control signal line and configured to control a first power supplied to the first memory sub-module;
• a second power management integrated circuit connected to a second power control signal line and configured to control a second power supplied to the second memory sub-module;
• a CXL controller configured to check whether read data from each of the first and second memory sub-modules is normal or abnormal;
• and
• a power controller connected to the first and second power management integrated circuits and configured to transmit first and second power control signals to the first and second power control signal lines, respectively,
• wherein the CXL controller is configured to generate a migration control signal based on a number of uncorrectable errors that occurred in the read data from the first memory sub-module,
• wherein the first memory sub-module is configured to transmit migration data stored in the first memory sub-module to the CXL controller through the CXL interface based on the migration control signal,
• wherein the second memory sub-module is configured to receive the migration data from the CXL controller through the CXL interface based on the migration control signal, and
• wherein the first power management integrated circuit is configured to block the first power to the first memory sub-module based on the first power control signal being an abnormality signal.