Atomic memory operations for address translation

A method comprising:

• generating a request on a bus to access an entry in a page table stored in a memory system, wherein the request includes an indication of whether an instruction that references an address being translated using the entry is a store instruction;
• receiving the request from the bus;
• accessing the entry in the page table, wherein the entry includes an accessed bit indicating whether a virtual page associated with the entry has been accessed since a last time the accessed bit was cleared and a dirty bit indicating whether the virtual page associated with the entry has been written to since a last time the dirty bit was cleared;
• as part of a single, uninterrupted operation responsive to the request, setting the dirty bit of the entry when the request includes the indication that the instruction is a store instruction;
• and
• transmitting contents of the entry on the bus in response to the request.

A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:

• a memory system including random access memory;
• a bus connected to the memory system;
• and
• an address translation engine connected to the bus, wherein the address translation engine is configured to:
• generate a request on the bus to access an entry in a page table stored in the memory system, wherein the request includes an indication of whether an instruction that references an address being translated using the entry is a store instruction;
• wherein the memory system is configured to:
• receive the request from the bus;
• access the entry in the page table, wherein the entry includes an accessed bit indicating whether a virtual page associated with the entry has been accessed since a last time the accessed bit was cleared and a dirty bit indicating whether the virtual page associated with the entry has been written to since a last time the dirty bit was cleared;
• as part of a single, uninterrupted operation responsive to the request, set the dirty bit of the entry when the request includes the indication that the instruction is a store instruction;
• and
• transmit contents of the entry on the bus in response to the request.